In front of you, you wrote it yourself, and I wrote key place reg [25: 0] CNT; //cnt is the counting register always @ (pose clk or neg edge rst _ n)// where clk is the 50M clock input if (! rst _ n)CNT & lt； = 26 ' d0else if(CNT = = 26 ' d 50000000)CNT & lt； = 26 ' d0else cnt & lt= CNT+ 1 ' b 1； I'm not familiar with verilog either. I think it should be written like this. If there are any mistakes, please advise. Thank you.