The gate circuit is controlled by the shaping signal with B channel input frequency fB, that is, one pulse opens the gate circuit and the next pulse closes the gate circuit. The time interval (TB) between two pulses is the door opening time. The pulse group with the shaping frequency fA input from channel A passes through the door within the door opening time, so that the counter counts, and the count value n = fa TB.

Subtraction operation rules; 0000- 1 can be regarded as (1) 0000-1=11; 111-1=110, and so on.

Note: The pin arrangement of 74LS 163 is the same as that of 74LS 16 1, but the difference is that 74LS 163 adopts synchronous zero clearing.

Logical function of CT74LS 16 1

①= 0, asynchronous clearing when C0=0.

②= 1, when =0, set the number of synchronous parallel bits.

③ When = = 1, CPT=CPP= 1, synchronous binary counting is performed according to 4-bit natural binary code.

④ When = = 1, CPT CPP = 0, the state of the counter remains unchanged.

Extended data:

In addition to the reset terminal, the reversible counter has two counting terminals, one is the positive counting terminal and the other is the negative counting terminal.

Its working condition is that when the initial state or reset terminal is on, the current value is 0 and it is not counted. The reset terminal is closed, allowing counting. Positive end from OFF to ON, positive counting, counting present value plus1; The negative terminal counts down from OFF to ON, and the current value of count is-1.

Reversible counters are sometimes needed in daily production and scientific research. For example, measure the final sinking depth of an object in water. Sometimes it has to be measured up and down several times. Obviously, the counter at this time should be reversible. This kind of counter that can calculate both addition and subtraction is called a reversible counter.

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