During the four years leading the 28nm technology, Xilinx has developed a new generation of design environment and tool suite, namely Vivado design suite. In terms of 20nm and 16nm process technologies, Xilinx continues to optimize FPGA, SoC and 3D IC with the new generation Vivado design suite. Through the simultaneous construction and optimization of tools, devices and IP, designers can maximize the value and performance of the chip and shorten the design and implementation process. 9. How does 9.ultrascale architecture cope with the challenge of massive data flow? Clock UltraScale architecture can solve the fundamental problems such as clock skew, a large number of bus layouts and system power management, achieve a very high new generation system speed, and effectively meet the challenges of massive data streams. Using the multi-area clock function of UltraScale similar to ASIC, designers can place the system-level clock in the best position (almost anywhere on the chip), which greatly reduces the skew of the system-level clock by 50%. The new generation interconnection architecture of Wiring UltraScale and Vivado software tools have been optimized cooperatively, and a real breakthrough has been made in programmable logic wiring. Xilinx focuses on understanding and meeting the requirements of new generation applications for massive data flow, multi-Gb intelligent packet processing, multi-Tb throughput and low latency. Through analysis, we come to the conclusion that interconnection has become the number one bottleneck affecting system performance at these data rates. Ultra-large-scale wiring architecture fundamentally eliminates the problem of wiring congestion. The conclusion is simple: as long as it is properly designed, there is no problem with layout and wiring. Power consumption Each generation of all series of programmable logic devices can significantly reduce the system-level power consumption, and the UltraScale architecture is built on this traditional advantage. Low power semiconductor technology and wide range of static and dynamic power gating realized by chip and software technology can reduce the total power consumption of the system to half of Xilinx's industry-leading 7-series FPGA (the lowest power consumption fully programmable device in the industry). 10. What additional advantages does Xilinx's stacked silicon chip interconnection technology (SSIT) bring to VLSI 3D IC? Virtex？ 0? 3 UltraScale and Kintex? 0? The number of connection function resources in 3 ultra scale series products and the inter-chip bandwidth in the second generation FPGA and 3D IC architecture are increasing step by step. The substantial increase of wiring and bandwidth and the optimized interface capacity of the latest 3D IC-wide memory can ensure that the new generation of applications can achieve the target performance with high device utilization. 1 1. When will the FPGA based on UltraScale architecture be launched? The early evaluation test version of Vivado design suite supporting UltraScale architecture FPGA has been released to customers in the 20 13 quarter. The first batch of UltraScale equipment will be launched in the fourth quarter of 20 13. 12 when? 16 nanometer products will be launched soon? With the accelerated development of TSMC, it is planned to provide 16nm FinFET test chips in the late 20 13 years, and launch the first batch of products in 20 14 years. 13. Why does Xilinx use "UltraScale" instead of following the 8-series naming rules? Very large scale architecture represents a turning point in PLD industry. The products manufactured by new technology nodes will expand Xilinx's entire product line. For PLD market, the increase of serial number is used to indicate the migration to the next technology node. Very large-scale architecture spans multiple technology nodes. Devices based on UltraScale architecture will coexist with 7 series devices. 14. How will the product names of Artix, Kintex and Virtex be affected? The name of the FPGA family will continue to be used in UltraScale or higher versions of technology. Artix？ 0? The naming of 3-7, Kintex-7 and Virtex-7 FPGA series will remain unchanged.