When in use, the input signal is connected to the CP pin, and the rising edge is valid; The clear terminal CR, the two enable terminals EP and ET, and the set terminal PE (also called LD) are all connected to the high level (power supply); All four data input terminals and carry terminal TC are empty; Q0~Q3 are frequency-divided outputs.

It should be noted that your input frequency signal must meet TTL requirements in amplitude, and it is best to use square wave. If it does not meet this requirement, it must be amplified or limited before shaping, so as to ensure the normal operation of the frequency divider.