Firstly, std_logic_vector(3 downto 0) is converted into integer type by conv_integer function in std_logic_unsigned package or std_logic_signed package, and then the objects (variables or signals) of integer type are respectively subjected to MOD 10 and REM 10 operations (modulo and remainder) to obtain the obtained results. If you still need to convert to std_logic_vector type, call conv_std_logic_vector function in std_logic_arith package to convert ten bits and one bit to std_logic_vector type respectively.

Of course, you can also describe a conversion module yourself, and it will be easier to directly divide std_logic_vector(3 downto 0) into ten bits and output one bit std_logic_vector(3 downto 0) respectively.