VHDL program
ErrorThe mismatch between std_logic_vector type and integer literal means that the main reason for the mismatch between STD _ logic _ vector type and plastic surgery is your Q 1

As for other grammatical mistakes, I don't need to go into details. I modified you directly in the program. Pay attention to the matching of if.

Library IEEE

Use IEEE. STD_LOGIC_ 1 164。 All;

Use IEEE. STD_LOGIC_ARITH。 All; -Add a library to use its functions.

Use IEEE. STD_LOGIC_UNSIGNED all;

The entity cnt3 15 is

PORT(clk,clrn:IN STD _ LOGIC;

q:out STD _ logic _ vector( 1 1 down to 0); -Define twelve digits

END CNT 3 15;

One of the architectures of cnt3 15 is

Signal q1:STD _ logic _ vector (3downto0);

Signal Q2: STD _ logic _ vector (3downto0);

Signal q3: STD_LOGIC_VECTOR (3 drops to 0);

begin

Process (clock, clock)

-variable cnt: integer range 0 to 315; I don't know why you set this variable.

begin

If(clrn =' 1') then

q 1 & lt; = "0000";

q2 & lt= "0000";

q3 & lt= "0000";

Elsif (clk' event and clk ='1') and then

If q 1= "0 100 "and q2= "000 1" and Q3 = "001/",then

q 1 & lt; = "0000" ;

q2 & lt= "0000" ;

q3 & lt= "0000" ;

Elsif q1= "1001"and then

q 1 & lt; = "0000";

If q2 = "100 1", then

q2 & lt= "0000";

Q3<= conv _ logic _ vector (conv _ integer (q3)+1, 4); -conv logical vector (x, y) x is the value and y is the size.

other

Q2<= conv _ logic _ vector (conv _ integer (q2)+1, 4);

End if;

other

q 1 & lt; = conv _ logic _ vector (conv _ integer (q 1)+1, 4);

End if;

q & lt= q3 & ampq2 & ampq 1;

End if;

End the process;

End one;