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Classification of integrated circuit packaging forms
1, BGA (ball grid array) spherical contact display, one of the surface mount packages. Spherical bumps are made on the back of the printed substrate instead of pins, LSI chips are assembled on the front of the printed substrate, and then sealed with molding resin or potting. Also known as bump display carrier (PAC). There can be more than 200 pins, which is the package of multi-pin LSI. The package can also be made smaller than QFP (quad pin flat package). For example, a 360-lead BGA with a pin center distance of 1.5mm is only 3 1mm square; A 304-pin QFP with a center-to-center distance of 0.5 mm is 40 mm2. And BGA doesn't have to worry about pin deformation like QFP. Developed by Motorola, the software package was first used in portable phones and other devices, and may be popularized in personal computers in the United States in the future. At first, the center distance between the pins (bumps) of BGA was 1.5mm, and the number of pins was 225. Now some LSI manufacturers are developing 500-pin BGA. The problem of BGA is visual inspection after reflow soldering. It is not clear whether this is an effective visual inspection method. Some people think that because of the great distance between welding centers, the connection can be regarded as stable and can only be handled through functional inspection. Motorola Company of the United States calls the package sealed with molding resin OMPAC and the package sealed with potting method GPAC (see OMPAC and GPAC).

2.BQFP (square flat package with bumper) Four-side pin flat package with buffer pad. One of QFP packages, bumps (buffer pads) are set at the four corners of the package to prevent the pins from bending and deforming during transportation. American semiconductor manufacturers mainly use this package in microprocessor, ASIC and other circuits. The pin center distance is 0.635 mm, and the number of pins ranges from 84 to 196 (see QFP).

3. Butt pin grid array is another name for surface mount PGA (see surface mount PGA). 4.C- (ceramic) indicates the sign of ceramic packaging. For example, CDIP stands for ceramic dipping sauce. This is a symbol that is often used in practice.

5.Cerdip adopts glass sealed ceramic dual in-line package, which is used in ECL RAM, DSP (Digital Signal Processor) and other circuits. Cerdip with glass window is used for ultraviolet erasing EPROM and microcomputer circuit with built-in EPROM. The pin center distance is 2.54mm, and the number of pins ranges from 8 to 42. In Japan, this package is called DIP-G(G stands for glass seal). 6. One of 6.Cerquad surface mount packages, namely ceramic QFP with lower seal, is used to package logic LSI circuits such as DSP. Cerquad with windows is used to package EPROM circuits. The heat dissipation is better than that of plastic QFP, and the power of 1.5 ~ 2W can be allowed under natural air cooling conditions. But the packaging cost is 3 ~ 5 times higher than that of plastic QFP. Pin center distance 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and other specifications. The number of pins ranges from 32 to 368.

7.CLCC (ceramic led chip carrier) is a ceramic chip carrier with pins, which is a kind of surface mount package. The pins are led out from four sides of the package in a T-shape. The window is used to encapsulate the ultraviolet erasable EPROM and the microcomputer circuit with EPROM. This package is also called QFJ and QFJ-g (see QFJ).

8.COB(chip on board) chip on board package is a kind of bare chip mounting technology. The semiconductor chip is attached to the printed circuit board, and the electrical connection between the chip and the substrate is realized by wire stitching, and the electrical connection between the chip and the substrate is realized by wire stitching and covered with resin to ensure reliability. Although COB is the simplest die mounting technology, its packaging density is far less than TAB and flip-chip bonding technology.

9.DFP (Double Flat Package) Double-sided pin flat package. It is another name for SOP (see SOP). This term has been used before, but it is basically not used now.

10, another name for DIC ceramic DIP (including glass seal) (see DIP).

1 1 and another name for DIL (dual in-line DIP) (see DIP). European semiconductor manufacturers often use this name.

12, DIP (dual inline package) dual inline package. In one package, pins are led out from both sides of the package, and the packaging materials are plastic and ceramics. DIP is the most popular plug-in package, and its application scope includes standard logic ic, memory LSI, microcomputer circuit and so on. The pin center distance is 2.54mm, and the number of pins varies from 6 to 64. The package width is usually 15.2 mm, and some packages with widths of 7.52mm and 10. 16mm are called skinny DIP and slim DIP respectively. But in most cases, it is not distinguished, simply called DIP. In addition, ceramic DIP sealed with low melting point glass is also called cerdip (see cerdip). 13, DSO (double small output lint) small package with two pins. Another name for SOP (see SOP). Some semiconductor manufacturers adopt this name.

14, DICP (dual carrier package) double-sided pin loading package. One of TCP (on-board encapsulation). The leads are made on the insulating tape and led out from both sides of the package. Because of the TAB technology, the package shape is very thin. Commonly used in LCD driver LSI, but mostly customized products. In addition, the memory LSI thin package with a thickness of 0.5mm is in the development stage. In Japan, DICP is named DTP according to EIAJ (Japan Electronic Machinery Industry) standard.

15 and DIP (double tape package) are the same as above. The nomenclature of DTCP in the standards of Japan Electronic Machinery Industry Association (see DTCP).

16, FP (flat package) flat package. One of the surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers adopt this name.

17, flip-chip flip-chip. One of the die packaging technologies is to make metal bumps in the electrode area of LSI chip, and then connect the metal bumps with the electrode area on the printed substrate by pressure welding. The package size is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, there will be reaction at the joint, which will affect the reliability of the connection. Therefore, it is necessary to reinforce LSI chips with resin and use substrate materials with basically the same thermal expansion coefficient.

18, FQFP (fine pitch square flat package) small pin center distance QFP. QFP (see QFP) with the center distance of guide foot less than 0.65 mm is usually used. Some conductor manufacturers adopt this name.

19, CPAC(globe top pad array carrier) is another name for BGA by Motorola (see BGA). 20.CQFP (square package with protective ring) quad pin flat package with protective ring. One of the plastic QFP pins is covered with a resin protection ring to prevent bending and deformation. Before the LSI is assembled on the printed board, the pins are cut off from the protective ring to make gull wings (L-shaped). This kind of packaging has been mass-produced in Motorola, USA. The pin center distance is 0.5mm, and the maximum number of pins is about 208.

2 1, H- (with radiator) indicates the mark with radiator. For example, HSOP stands for SOP with radiator. 22. Pin grid array (surface mount type) surface mount PGA. Usually, PGA is a plug-in package with a pin length of about 3.4 mm Surface mount PGA has a display-like pin at the bottom of the package with a length range of1.5 mm-2.0 mm. It is also called bump welding PGA because it is mounted by bump welding with printed substrate. Because the pin center distance is only 1.27mm, which is half smaller than the plug-in PGA, the package can be made smaller and the number of pins is more than that of the plug-in PGA (250 ~ 528), so it is the package of large-scale logic LSI. The packaging substrate includes multilayer ceramic substrate and glass epoxy resin printed substrate. Packaging made of multilayer ceramic substrates has been put into practical use.

23.JLCC (J-led chip carrier) J- pin chip carrier. It refers to the nicknames of CLCC with window and ceramic QFJ with window (see CLCC and QFJ). A name adopted by some semiconductor manufacturers.

24. LCC (leadless chip carrier) leadless chip carrier. Refers to the surface mount package in which the four sides of the ceramic substrate are only in contact with the electrodes and there are no leads. This is a high-speed high-frequency integrated circuit package, also known as ceramic QFN or QFN-C (see QFN).

25.LGA (grid array) contact display module. That is, a package having flat electrode contacts in an array state is manufactured on the bottom surface. Just insert the socket when assembling. Ceramic LGA with 227 contacts (1.27 mm center distance) and 447 contacts (2.54 mm center distance) has been applied to high-speed logic LSI. Compared with QFP, LGA can accommodate more input and output pins in a smaller package. In addition, because the impedance of the lead is very small, it is very suitable for high-speed LSI But because of the complexity and high cost of the socket, it is basically not used now. It is expected that the demand for it will increase in the future.

26.LOC (Lead on Chip) Lead packaging on the chip. One of LSI packaging technologies, the front end of the lead frame is above the chip, and a bump solder joint is made near the center of the chip, and the electrical connection is realized by wire splicing. Compared with the original structure in which the lead frame is arranged near the side of the chip, the width of the chip contained in the same size package is about1mm.

27.LQFP (thin quad flat package) thin QFP. QFP with package thickness of 1.4mm is the name used by Japan Electronic Machinery Industry Association according to the new QFP shape specification.

28. One of QFP L-Quad ceramics. The thermal conductivity of aluminum nitride used for packaging substrate is 7 ~ 8 times higher than that of alumina, and it has good heat dissipation. The packaging frame is made of alumina, and the chip is sealed by potting, thus suppressing the cost. It is a package developed for logic LSI, which can withstand the power of W3 under natural air cooling. At present, LSI logic packages with 208 pins (center distance 0.5mm) and 160 pins (center distance 0.65mm) have been developed and put into mass production in1June 1993.

29.MCM (multi-chip module) multi-chip module. A package in which a plurality of bare semiconductor chips are assembled on a wiring substrate. According to the substrate materials, it can be divided into three categories: MCM-L, MCM-C and MCM-D. MCM-L is assembled by ordinary glass epoxy multilayer printed substrates. The wiring density is not very high and the cost is low. MCM-C is an element that uses thick film technology to form multilayer wiring with ceramics (alumina or glass ceramics) as the substrate, which is similar to thick film hybrid integrated circuits with multilayer ceramic substrates. There is no obvious difference between the two. The wiring density is higher than that of MCM-L. MCM-D is a multilayer wiring formed by thin film technology, with ceramics (alumina or aluminum nitride) or Si and Al as substrate components. Wiring collusion is the highest among the three components, but the cost is also high.

30, MFP (mini flat packaging) small flat packaging. Another name for plastic SOP or SSOP (see SOP and SSOP). A name adopted by some semiconductor manufacturers.

3 1, MQFP (metric quad flat package) is a QFP classification according to JEDEC (united electronic equipment committee) standard. Guide standard QFP, center distance 0.65mm, body thickness 3.8 mm ~ 2.0 mm (see QFP). 32. A QFP package developed by American Olin Company. Both the base plate and the cover are made of aluminum and sealed with adhesive. In the case of natural air cooling, the power of 2.5W~2.8W can be allowed. Shin Kong Electric Industry Co., Ltd. of Japan obtained the production license on 1993.

33.MSP(mini square package) QFI is another name (see QFI), which was often called MSP in the early stage of development. QFI is the name stipulated by Japan Electronic Machinery Industry Association.

34.OPMAC (Overmolded Pad Array Carrier) molded resin sealed bump display carrier. The name of the molded resin sealed BGA adopted by Motorola, USA (see BGA).

35.P- (plastic) indicates the sign of plastic packaging. For example, PDIP stands for plastic dip.

36.PAC (pad array carrier) bump display carrier, another name for BGA (see BGA).

37. PCLP (Lead-free Package of Printed Circuit Board) Lead-free Package of Printed Circuit Board. The name of plastic QFN (Plastic LCC) used by Fujitsu Company of Japan (see QFN). The center distance of the guide foot is 0.55mm and 0.4 mm.. It is currently in the development stage.

38.PFPF (Plastic Flat Packaging) Plastic Flat Packaging. Another name for plastic QFP (see QFP). A name adopted by some LSI manufacturers.

39.PGA (Pin Grid Array) display pin package. One of the plug-in packages has vertical pins arranged in an array on its bottom surface. Basically, the packaging substrate adopts multilayer ceramic substrates. Most of them are ceramic PGA, which is used in high-speed large-scale logic LSI circuits. The cost is higher. The pin center distance is usually 2.54mm, and the number of pins varies from 64 to 447. In order to reduce the cost, the packaging substrate can be replaced by glass epoxy printed substrate. And 64 ~ 256 needles of plastic pg a. In addition, there is a short pin surface mount PGA (bump bonded PGA) with a pin center distance of 1.27 mm (see surface mount PGA).

40, backpack. Refers to the ceramic package with socket, similar to DIP, QFP and QFN. It is used to evaluate the program validation operation when developing equipment with microcomputer. For example, plug the EPROM into the socket for debugging. This kind of packaging is basically customized and is not very popular in the market.

4 1, PLCC (plastic Led chip carrier) Plastic chip carrier with leads. One of the surface mount packages. The pins are led out from the four sides of the package, which are T-shaped and are plastic products. Texas Instruments was first used in 64k-bit DRAM and 256kDRAM, and now it has been widely used in logic LSI, DLD (or program logic device) and other circuits. The center distance of needles is 1.27mm, and the number of needles varies from 18 to 84. J-pin is not easy to deform and is easier to operate than QFP, but it is more difficult to check the appearance after welding. PLCC is similar to LCC (also known as QFN). In the past, the only difference between the two was that the former used plastic and the latter used ceramics. However, J-lead package made of ceramic and leadless package made of plastic (labeled as plastic LCC, PC LP, P-LCC, etc.) have appeared. ), has been unable to distinguish. Therefore, Japan Electronic Machinery Industry Association decided in 1988 to call the package with J-shaped leads on four sides as QFJ and the package with electrode bumps on four sides as QFN (see QFJ and QFN).

42.P-LCC (plastic contactless chip carrier) (plastic Led chip carrier) is sometimes another name for plastic QFJ and sometimes another name for plastic QFN (plastic LCC) (see QFJ and QFN). Some LSI manufacturers use P-LCC for lead packaging and P-LCC for leadless packaging to show the difference.

43.QFH (quad flat high package) quad pin thick flat package. A kind of plastic QFP, in order to prevent the package from cracking, the QFP body is made thicker (see QFP). A name adopted by some semiconductor manufacturers.

44.qfi (quad flat I-led package GAC) quad I-pin flat package. One of the surface mount packages. The pins are led out from the four sides of the package, and they are downward I-shaped. Also known as MSP (see MSP). The mounting piece is connected with the printed substrate by bump welding. Because the pin has no protruding part, the surface area occupied by the installation is smaller than QFP. Hitachi developed and used this package for video analog IC. In addition, the PLL integrated circuit of Motorola in Japan also adopts this package. The needle center distance is 1.27mm, and the number of needles varies from 18 to 68.

45.QFJ (square flat j-led package) four-sided J-pin flat package. One of the surface mount packages. The pins are led out from four sides of the package and are J-shaped downward. It is the name stipulated by Japan Electronic Machinery Industry Association. The center distance of the pin is 1.27mm, and it is made of plastic and ceramic. In most cases, plastic QFJ is called PLCC (see PLCC), which is used in microcomputer, gate display, DRAM, ASSP, OTP and other circuits. The number of pins ranges from 18 to 84. Ceramic QFJ is also called CLCC and JLCC (see CLCC). The package with window is used for ultraviolet erasing EPROM and microcomputer chip circuit with EPROM. The number of pins ranges from 32 to 84.

46. QFN (quad flat non-led package) is flat and leadless on all sides. One of the surface mount packages. It is often called LCC now. QFN is the name stipulated by Japan Electronic Machinery Industry Association. Four sides of the package are equipped with electrode contacts. Because there are no pins, the installation area is smaller than QFP and the height is lower than QFP. However, when stress occurs between the printed substrate and the package, it cannot be released at the electrode contact. Therefore, it is difficult to make as many electrode contacts as QFP pins, generally from 14 to 100. There are two kinds of materials: ceramics and plastics. When there is an LCC logo, it is basically a ceramic QFN. The distance between electrode contact centers is1.27mm.. Plastic QFN is a low-cost glass epoxy printed substrate package. In addition to 1.27mm, there are two kinds of electrode contact center distances of 0.65mm and 0.5mm. This package is also called plastic LCC, PCLC, P-LCC, etc. 47.QFP (Square Flat Package) quad pin flat package. In a surface mount package, leads are led out from four sides in the shape of gull wings (L). There are three kinds of substrates: ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When no material is specified, it is plastic QFP in most cases. Plastic QFP is the most popular multi-pin LSI package. It is not only used in digital logic LSI circuits such as microprocessors and gate displays, but also used in analog LSI circuits such as VTR signal processing and audio signal processing. Pin center distance 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and other specifications. The maximum number of pins in the 0.65mm center-to-center distance specification is 304. In Japan, QFP with needle center distance less than 0.65 mm is called QFP. But now Japan Electronic Machinery Industry Association has re-evaluated the external specifications of QFP. There is no difference in pin center distance, but it can be divided into three types according to the package thickness: QFP (2.0 mm ~ 3.6 mm thick), LQFP( 1.4mm thick) and TQFP( 1.0mm thick). In addition, some LSI manufacturers refer to QFP with a pin center distance of 0.5 mm as shrinking QFP or SQFP and VQFP. However, some manufacturers refer to QFP with pin center distance of 0.65mm and 0.4mm as SQFP, which makes the name a bit confusing. The disadvantage of QFP is that when the center distance of the pin is less than 0.65mm, the pin is easy to bend. In order to prevent pin deformation, several improved QFP varieties have appeared. Such as packaging BQFP with tree finger pads at four corners (see BQFP); GQFP, the front end of the pin is covered with a resin protection ring (see Gqfp); Tppqfp (see tppqfp) can be tested by setting test bumps in the package and placing them in special fixtures to prevent pin deformation. In logic LSI, many developed products and high reliability products are packaged in multilayer ceramic QFP. The product with the minimum pin center distance of 0.4mm and the maximum number of pins of 348 also came out. In addition, ceramic QFP sealed with glass is provided (see Gerqa d).

48. QFP (QFP fine pitch) Small center distance QFP. The name specified in the standards of Japan Electronic Machinery Industry Association. QFP (see QFP) with the center distance of guide pin less than 0.65mm, such as 0.55mm, 0.4mm, 0.3mm, etc.

49. Another name for QFP of QIC ceramics. A name adopted by some semiconductor manufacturers (see QFP and Cerquad).

50, QIP(quad in-line plastic package) plastic QFP another name. A name adopted by some semiconductor manufacturers (see QFP).

5 1, QTCP (quad tape package) quad pin loading package. A TCP package, pins are formed on an insulating tape and lead out from four sides of the package. It is a thin package that benefits from TAB technology (see TAB, TCP).

52.QTP (Quadruple Carrier Tape Package) quad pin loading package. The name used by Japan Electronic Machinery Industry Association for the shape specification of QTCP in April 1993 (see TCP).

53.QUIL (four-way in-line) is another name for QUIP (see Quip).

54.QUIP (quad in-line package) quad in-line package. The pins are led out from both sides of the package, and every other pin is staggered and bent down into four columns. The center-to-center distance of the pin is1.27mm, and when the pin is inserted into the printed circuit board, the center-to-center distance becomes 2.5mm. Therefore, it can be used for standard printed circuit boards. This is a smaller package than the standard DIP. NEC has adopted some kind of package in microcomputer chips such as desktop computers and household appliances. There are two kinds of materials: ceramics and plastics. The number of pins is 64. 55. The shrinkage of SDIP (shrink dual in-line package) decreased. One of the plug-in packages has the same shape as DIP, but the pin center distance (1.778mm) is smaller than DIP(2.54 mm), so it is called this. The number of pins ranges from 14 to 90. And those named sh-dip. There are two kinds of materials: ceramics and plastics.

56.Sh-dip is the same as SDIP. A name adopted by some semiconductor manufacturers. 57. Another name for SIL (Single Inline SIP) (see SIP). The name SIL is often used by European semiconductor manufacturers. 58.SIMM (single-row in-line memory module) single-row memory module. A memory module is provided with electrodes only near one side of a printed substrate. Usually refers to a component inserted into a socket. The standard SIMM has two specifications: 30 electrodes with a center-to-center distance of 2.54mm and 72 electrodes with a center-to-center distance of 1 .27 mm. SIMM with SOJ packaging1megabit and 4 megabit DRAM on one or both sides of the printed substrate has been widely used in personal computers, workstations and other equipment. At least 30 ~ 40% of DRAM is assembled in SIMM.

59. SIP (Single in-line package) Single in-line package. The pins are led out from one side of the package and arranged in a straight line. When assembled on a printed substrate, the package is upright. The pin center distance is usually 2.54mm, and the number of pins varies from 2 to 23, most of which are customized products. The shapes of packages are different. Others call a package with the same shape as ZIP SIP.

60. A sk-dip (thin dual in-line package) dip. Refers to the narrow inclination angle with a width of 7.62 mm and a pin center distance of 2.54 mm. Usually called dip angle (see dip angle).

6 1 and SL-dip (ultra-thin dual in-line package) dip. Refers to the narrow inclination angle with the width of 10. 16 mm and the pin center distance of 2.54 mm. It is generally called DIP.

62.SMD (surface mount device) surface mount device. Occasionally some semiconductor manufacturers classify SOP as SMD (see SOP).

63. Another name for so (small perimeter) SOP. Many semiconductor manufacturers in the world adopt this nickname. (see SOP). 64. SOI (small outgoing I-led package) I-pin small outline package. One of the surface mount packages. The pins are led down from both sides of the package in an I-shape, with the center distance of 1.27 mm, and the mounting area is smaller than SOP. Hitachi adopted this package in analog IC (motor drive IC). The number of leads is 26.

65. Another name for 65.SOIC (small peripheral integrated circuit) SOP (see SOP). Many foreign semiconductor manufacturers adopt this name.

66. SOJ (small outgoing line j-led package) J-pin small package. One of the surface mount packages. The pins are led out from both sides of the package and are J-shaped downward, hence the name. Usually plastic products, mostly used in memory LSI circuits such as DRAM and SRAM, but most of them are DRAM. Many DRAM devices packaged with SO J are assembled on SIMM. The needle center distance is 1.27mm, and the number of needles ranges from 20 to 40 (see SIMM).

67.SQL (small outgoing l-led package) adopts the name of SOP according to JEDEC (Joint Electronic Equipment Engineering Committee) standard (see SOP).

68. Small perimeter without heat sink without heat sink SOP. Same as usual SOP. In order to show the difference of no heat sink in power IC package, NF (Finless) mark is specially added. A name adopted by some semiconductor manufacturers (see SOP).

69. SOF (Small Outgoing Package) Small Profile Package. A surface mount package, the leads are led out from both sides of the package in a gull-wing shape (L shape). There are two kinds of materials: plastic and ceramic. Also known as SOL and DFP. SOP is not only used in memory LSI, but also widely used in ASSP and other small-scale circuits. SOP is the most popular surface mount package in the field where the input and output terminals do not exceed 10 ~ 40. The pin center distance is 1.27mm, and the number of pins ranges from 8 to 44. In addition, the SOP with pin center distance less than 1.27mm is also called SOP; SOP with assembly height less than 1.27mm is also called TSOP (see SSOP and TSOP). And SOP with heat sink.

70.SOW (Wide-JYPE) wide-body SOP. A name adopted by some semiconductor manufacturers.

7 1 and COB (chip on board) fix the IC die on the printed circuit board by bonding. That is to say, the chip is directly bonded to the PCB, and the electrical connection between the chip and the PCB is realized by wire bonding, and then it is encapsulated with vinyl. The key technologies of COB are wire bonding (commonly known as wire bonding) and molding (packaging molding), which refers to the process of packaging bare ic chips to form electronic components, in which the bonding of IC adopts wire bonding, flip chip bonding or tape automatic bonding; ; Techniques such as abbreviation (TAB) expand its I/O through packaged circuits. Cog (Chip on Glass) is an increasingly practical packaging technology in the world. Packaging technology which has great influence on the development of liquid crystal display technology.