what exactly is JTAG?

JTAG(Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible), which is mainly used for internal testing of chips. At present, most advanced devices support JTAG protocol, such as DSP and FPGA devices. The standard JTAG interface is 4 wires: TMS, TCK, TDI and TDO, which are mode selection, clock, data input and data output wires respectively.

JTAG was originally used to test the chip. The basic principle is to define a TAP(Test Access Port) inside the device to test the internal nodes through a special JTAG test tool. JTAG test allows multiple devices to be connected in series through JTAG interface to form a JTAG chain, which can test each device separately. Now, JTAG interface is also commonly used to realize ISP(In-System rogrammable Online Programming) and program devices such as FLASH.

JTAG programming mode is online programming. In the traditional production process, the chip is pre-programmed first and then mounted on the board, which changes it. The simplified process is to fix the device on the circuit board first and then program with JTAG, which greatly speeds up the project progress. JTAG interface can program all components inside PSD chip

Some descriptions of JTAG

JTAG is generally divided into two categories, one is used to test the electrical characteristics of the chip and detect whether there is any problem with the chip; One is used for debugging; Generally, these two modules are included in the CPU supporting JTAG.

as long as the clock is normal, a CPU with JTAG Debug interface module can access the internal registers of the CPU and devices hanging on the CPU bus through JTAG interface, such as registers of built-in modules of FLASH, RAM and SOC (such as 451B, 44Box and AT91M series), such as registers of UART, Timers and GPIO.

the above is only the capabilities of JTAG interface. To use these functions, you need the cooperation of software, and the specific functions are determined by the specific software.

for example, the function of downloading progRAMs to ram. Anyone who knows about SOC knows that to use external RAM, you need to refer to the register description of SOC DataSheet and set the base address, bus width, access speed and so on of RAM. Some SoCs need Remap to work properly. When you run Firmware, these settings are completed by Firmware's initialization program. However, if JTAG interface is used, the related registers may still be at the power-on value, or even at the wrong value, and the RAM cannot work normally, so the download is bound to fail. To use it normally, we must first find a way to set up RAM. In ADW, it can be Set by the Let command in the Console window, and in AXD, it can be set by the set command in the Console window.

PLL is the abbreviation of Phase-Locked Loop, which means phase-locked loop in Chinese. PLL is basically a closed-loop feedback control system, which can make the output of PLL keep a fixed phase relationship with a reference signal. PLL generally consists of a phase detector, a Charge Pump, a low-pass filter, a voltage-controlled oscillator, and some form of output converter. In order to make the output frequency of PLL a multiple of the reference clock, a frequency divider can also be placed on the feedback path or (and) the reference signal path of PLL.