Can be understood as the same, timing blocks are usually controlled by clock clk, such as registers:

always @ (posedge clk or negedge rst_n)

if (~rst_n)

out <= 1'b0;

else

out <= in;

The output is only in clk It will change only on the rising edge, that is, it will become the stable input value before the rising edge of clk.

The synchronized block also means the same, the output is synchronized with the clock.

The reset signal in the always block is divided into synchronous reset and asynchronous reset. Those with negedge rst_n in the sensitivity list are asynchronous resets, while those without are synchronous resets.

As follows: (The output must change on the rising edge of the clock, even if the reset signal changes)

always @ (posedge clk)

if (~rst_n)

out <= 1'b0;

else

out <= in;