The world's largest chip maker promises to achieve significant performance and efficiency improvement in the next decade, which they attribute to the same method: transistor stacking.
IBM and Samsung demonstrated a new technology of vertically stacking transistors at the IEDM conference in San Francisco. The two companies claim that this method will improve performance or efficiency. In addition, at the same meeting, Intel described a method of stacking transistors in 3D direction to fit a given space.
Intel has often mentioned that it wants to continue the trend established by Moore's Law. Gordon Moore's observation in 1965 shows that the number of transistors in integrated circuits doubles about every two years. For decades, the semiconductor industry has been operating under this premise, pushing the chip size down every other year. However, this complexity has forced companies such as Intel to postpone the transition to more advanced microarchitecture. As far as Intel is concerned, this means falling behind competitors and losing well-known customers, including Apple. With the increasing difficulty of shrinking chips, chip manufacturers are looking for new ways to upgrade the core components of modern computing.
The current chip is flat on the surface of silicon, and the current flows horizontally from the metal layer to the source. Using the technology described by Samsung /IBM and Intel, the transistors will be one above the other and the current will flow vertically. According to Intel, stacking NMOS and PMOS transistors together instead of placing them side by side can increase the number of transistors in a given area by 30% to 50%. More transistors mean executing more complex instructions.
PaulFischer, director and senior chief engineer of Intel's component research department, said in an interview with Reuters: "By stacking the devices directly together, we obviously save area." "We are reducing the interconnection length and really saving energy, making it not only more cost-effective, but also better in performance."
On the other hand, Samsung and IBM call their technology VTFET, and claim that it can provide twice the performance or 85% energy efficiency improvement compared with FinFET design. The two companies say that stacking enables them to overcome performance limitations or complete the process with less energy waste.
Key point: According to Engadget, IBM and Samsung claim that this may one day lead to a week-long smart charging. Specific energy-consuming tasks such as encryption mining can significantly improve efficiency, which will reduce the carbon footprint.
We are still in the early stage of this technology, and we need to solve several potential obstacles-thermal management is one of them-to make it a feasible solution. There is no timetable for the arrival of the first batch of vertically stacked transistor chips, but don't expect it to come soon. 20 1 1 year, Intel switched from planar MOSFET design to FinFET, which is a 3D structure and can achieve higher energy efficiency.
Earlier this year, Intel said it would switch its Intel 20A chip to a new transistor design called RibbonFET in 2024. This upcoming structure uses a strip channel surrounded by a gate to achieve faster performance with smaller size. Vertical stacking will be the next potential move-it can open a new era of high-performance or low-energy computing.