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How does Verilog use division?
The ip core using divider in ISE should be called out, and the divider number cannot be synthesized directly.

It is impossible to synthesize circuits by writing multiplication and division symbols directly in HDL, which is a grammar for accessing truth.

Verilog HDL is a hardware description language (HDL), which describes the structure and behavior of digital system hardware in text form. It can be used to represent the logic circuit diagram, logic expression and logic function completed by digital logic system. Verilog HDL and VHDL are the two most popular hardware description languages in the world, both of which were developed in the mid-1980s. The former was developed by Gateway Design Automation Company (which was acquired by Cadence Company in 1989). Both HDL are IEEE standards.