Phase loop technology
The theory of phase-locked technology was put forward as early as 1932, but it was not widely used in TV until 1940s. The full name of PLL in English is PLL, which is a negative feedback system to realize automatic phase control. It synchronizes the phase and frequency of the oscillator with that of the input signal.
Phase-locked loop consists of three main parts: ① Phase detector loop (or phase comparator, named PD or PC): it is the unit that completes phase comparison and is used to compare the phases of input signal and reference signal. Its output voltage is proportional to the phase difference between the two input signals. ② Low-pass filter (LPF): It is a linear circuit, and its function is to filter out the high-frequency components in the output voltage of the phase detector, thus playing the role of smooth filtering. It usually consists of resistance, capacitance or inductance. ⑶ Voltage-controlled oscillator (VCO): An oscillator whose oscillation frequency is controlled by a control voltage, and the oscillation frequency has a linear relationship with the control voltage. In PLL, VCO actually converts the control voltage into phase.
Figure 1 is a block diagram of PLL composed of the above three parts. Its working process is as follows: the phase comparator compares its frequency and phase with the signal sent from the output end of VCO based on the input signal. If any phase (frequency) difference is detected within its working range, an error signal Ve(t) will be generated, which is proportional to the phase difference between the input signal and the VCO output signal, and is usually a DC level modulated by an AC component. The AC component in the error signal is filtered by the low-pass filter, and a signal Vd(t) is generated to control the VCO, forcing the VCO to change its frequency in the direction of reducing the phase/frequency error, so that any frequency or phase difference between the input reference signal and the VCO output signal gradually decreases until it is zero. At this point, we call it loop locking.
If the output frequency of VCO is lower than the frequency of input reference signal, the output amplitude of phase comparator is positive. After filtering, the VCO is controlled to increase its frequency until the frequency and phase of the two signals are accurately synchronized. Conversely, if the output frequency of the VCO is higher than the input reference signal, the output of the phase comparator will drop, so that the VCO is locked at the frequency of the input reference signal.
The capture process and tracking status are described in detail below.
Assuming that there is no control signal input, the natural oscillation frequency of VCO is Wo. After startup, if the input signal frequency Wi of the phase comparator is very close to Wo, the phase comparator will output beat waves of these two frequency signals. Because of its low frequency, it will pass through the low-pass filter smoothly and then be applied to the input of VCO as a control voltage. The VCO is frequency-modulated by this beat, and the center frequency is still Wo. The FM signal immediately returns to the phase comparator, and there is a DC component in its output signal, which is taken out through the integration of the low-pass filter and added to the input end of the VCO, thus shifting the center frequency of the VCO. This offset direction just moves towards the frequency Wi of the input signal, which makes the frequency of the beat signal output by the phase comparator lower and lower, and the DC component of the phase difference will become larger and larger. This gradually increasing DC component controls the VCO through a low-pass filter, so that the oscillation frequency of the VCO tends to Wi at a faster speed.
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The meaning of PLL is the automatic control of phase synchronization. The automatic control closed-loop system that can complete the phase synchronization of two electric signals is called phase locked loop, or PLL for short. It is widely used in broadcast communication, frequency synthesis, automatic control and clock synchronization. The PLL is mainly composed of a phase comparator and a voltage controlled oscillator. The low-pass filter consists of three parts, as shown in figure 1.
Figure 1
The output u0 of VCO is connected to the input of the phase comparator, and its output frequency is determined by the average voltage Ud established on the low-pass filter. An external input signal Ui applied to the other input terminal of the phase comparator is compared with an output signal Uo from a voltage controlled oscillator, and an error output voltage U psi generated as a result of the comparison is proportional to the phase difference between the two signals Ui and Uo, and an average voltage Ud is obtained after filtering out high-frequency components by a low-pass filter. The average voltage Ud changes in the direction of reducing the difference between the VCO output frequency and the input frequency until the VCO output frequency coincides with the input signal frequency. At this time, the frequencies of the two signals are the same, and the phase difference of the two signals remains unchanged (that is, synchronization), which is called phase locking.
Figure 2
When the PLL is locked, it also has the ability to "capture" the signal. VCO can automatically track the change of input signal within a certain range. If the input signal frequency changes within the capture range of the PLL, the PLL can capture the input signal frequency and force the VCO to lock at this frequency. The application of PLL is very flexible. If the input signal frequency f 1 is not equal to the VCO output signal frequency f2, it is required to maintain a certain relationship between them, such as proportional relationship or differential relationship, and an operator can be added externally to meet the needs of different jobs. In the past, PLL was mostly composed of discrete components and analog circuits. Nowadays, the phase-locked loop of integrated circuits is often used. CD4046 is a general CMOS PLL integrated circuit, which is characterized by wide power supply voltage range (3 V- 18 V), high input impedance (about 100 mω) and low dynamic power consumption. At the center frequency f0 of 10kHz, the power consumption is only 600μ W. Figure 2 shows the pin arrangement of CD4046, which adopts 16 pin dual in-line type, and the functions of each pin are as follows:
1 pin phase output, which is high when the loop is locked and low when the loop is unlocked. Output terminal of 2-pin phase comparator I. 3-pin comparison signal input. 4-pin VCO output. 5-pin terminal prohibition, high level prohibition, low level permission to work. 6, 7 pin external oscillation capacitor. 8. Negative terminal and positive terminal of16 pin power supply. Control terminal of 9-pin voltage controlled oscillator. 10 pin demodulation output terminal for FM demodulation. 1 1 and 12 pins are externally connected with oscillating resistors. 13 output terminal of pin phase comparator II. 14 pin signal input. The 15 pin has an independent zener voltage regulator negative electrode.
Figure 3
Fig. 3 is the internal electrical principle block diagram of CD4046, which is mainly composed of phase comparison I and II, voltage controlled oscillator (VCO), linear amplifier, source follower and shaping circuit. Comparator I adopts XOR gate structure. When the level states of the two input signals Ui and Uo are different (that is, one is high level and the other is low level), the output signal U ψ is high level; Conversely, when the Ui and Uo level states are the same (that is, both are high level or low level), the U ψ output is low level. When the phase difference Δ φ between Ui and Uo changes in the range of 0- 180, the pulse width m of U ψ also changes, that is, the duty cycle also changes. From the input and output signal waveforms of comparator I (as shown in Figure 4), it can be known that the frequency of its output signal is equal to twice that of the input signal, and it keeps a 90-degree phase shift with the central frequency between the two input signals. It can also be seen from the figure that fout is not necessarily a symmetrical waveform. For phase comparator I, it requires the duty cycle of Ui and Uo to be 50% (square wave) to maximize the locking range.
Figure 4
Phase comparator II is a digital storage network controlled by the rising edge of the signal. It does not require a high duty cycle of the input signal and allows the input of asymmetric waveforms. It has a wide capture frequency range and will not lock the harmonics of the input signal. It provides two outputs: digital error signal and locking signal (phase pulse). When locking is achieved, the phase shift between the two input signals of the phase comparator II remains 0.
For phase comparator II, when the frequency of 14 pin input signal is lower than that of 3 pin comparison signal, the output is logic "0"; Otherwise, the logic "1" is output. If the two signals have the same frequency but different phases, the phase comparator II outputs a positive pulse when the phase of the input signal lags behind the comparison signal, and a negative pulse when the phase leads. In both cases, a negative pulse with the same width as the above-mentioned positive and negative pulses is generated from the 1 pin. The width of the positive and negative pulses output from the phase comparator II is equal to the phase difference between the rising edges of the two input pulses. When the frequency and phase of the two input pulses are the same, the output of the phase comparator II is high impedance state, and the pin 1 outputs a high level. The above waveform is shown in fig. 5. It can be seen that whether the output signal of the 1 pin is a negative pulse or a fixed high level can determine the situation of the two input signals.
Figure 5
The phase-locked loop of CD4046 adopts RC voltage-controlled oscillator, which must be externally connected with capacitor C 1 and resistor R 1 as charging and discharging elements. When the PLL needs to track the frequency width of the input signal, it also needs an external resistor R2. Since VCO is a current-controlled oscillator, the charging current of timing capacitor C 1 is proportional to the control voltage input from pin 9, so the oscillation frequency of VCO is also proportional to the control voltage. When the VCO control voltage is 0, its output frequency is the lowest; When the input control voltage is equal to the power supply voltage VDD, the output frequency linearly increases to the highest output frequency. The oscillation frequency range of VCO is determined by R 1, R2 and C 1. Because it is charged and discharged by the same capacitor C 1, its output waveform is a symmetrical square wave. Generally, the highest frequency of CD4046 is 1. 2MHz(VDD= 15V), if VDD
There is also a linear amplifier and shaping circuit in the CD4046, which can change the weak input signal of about1000 mv input at the 14 pin into a square wave or pulse signal and send it to a two-phase comparator. The source tracker is an amplifier with a gain of 1, and the output voltage of VCO is FM demodulated through the source tracker to the 10 pin. Zener diode can be used alone, and its regulating voltage is 5V. If matched with TTL circuit, it can be used as an auxiliary power supply.
To sum up, the working principle of CD4046 is that the input signal Ui is input from 14 pin, amplified and shaped by amplifier A 1, and then added to the input terminals of phase comparators I and II. When the switch k in fig. 3 is turned to pin 2, the comparator I compares the phase of the comparison signal Uo input from pin 3 with the input signal Ui, and the error voltage U ψ output from the phase comparator reflects both. U ψ is filtered by R3, R4 and C2 to obtain the control voltage Ud, which is applied to the input end 9 of the voltage-controlled oscillator VCO, and the oscillation frequency f2 of the VCO is adjusted to make f2 quickly approach the signal frequency f 1. The output of VCO passes through the frequency divider, and then enters the phase comparator I to continue the comparison with Ui. Finally, F2 = F 1, and the phase difference between them is a certain value, thus realizing phase locking. If the switch K is set to the 13 pin, the phase comparator II will work, and the process is the same as above, so I will not repeat it.