Speaking of bus, it may include many old birds who are not very clear about its context. Let's take a look!
The CPU needs to exchange data with various peripheral hardware devices. If each device introduces a set of lines directly connected to the CPU, the system lines will be disordered. In order to simplify the hardware circuit and system structure, a set of data transmission lines (buses) for various devices are introduced into the computer. The CPU is connected with various peripheral hardware devices through the bus, and exchanges data through the bus. That is to say, the bus is a common channel for transmitting data between components in the computer.
First, the bus performance parameters
The main performance parameters of bus are bus bandwidth, bus bit width and bus working clock frequency.
1. bus bandwidth
Bus bandwidth, also known as bus transmission rate, is used to describe the speed at which the bus transmits data. Expressed by the amount of data that can be transmitted per unit time (per second) on the bus, the commonly used unit is MB/s, for example, the bandwidth of AGP bus conforming to AGP 2× specification is 528 MB/s.
2. Bus bit width
Bus bit width refers to the amount of data that the bus can transmit binary numbers at a time, and the unit is bits. We often say that 32 bits and 64 bits refer to the bus width. The greater the bit width of the bus, the more data will be transmitted through the bus at a time, and the greater the bus bandwidth.
3. Bus working clock frequency
Bus working clock frequency is referred to as bus clock for short, which is used to describe the working speed of the bus. It is expressed by the number of times that data can be transmitted per unit time (per second) on the bus, and the common unit of bus clock is MHz. The higher the bus clock frequency, the more times the data is transmitted through the bus per unit time, and the greater the bus bandwidth.
Because different devices in the computer have different speeds and require different amounts of data, the bus clocks leading to different devices are also different. It is necessary to provide the system clock (a fairly accurate and stable pulse signal generator generated by a crystal oscillator installed on the motherboard) to different devices and buses through frequency division.
For example, for a system with 133 MHz external frequency P Ⅲ CPU motherboard, the system clock is 133 MHz, and the external bus and internal bus of CPU work at133mhz; The AGP channel works at 66mhz (133x1/2mhz, divided by two); PCI bus works at 33mhz (133x1/4mhz, divided by four), and the working clocks of AGP and PCI are generated by frequency dividing circuit. (From the frequency division, we can see why sometimes our overclocking to 75MHz and 83MHz is called nonstandard external frequency? Because such external frequencies can't be averaged after frequency division, the computer can't work stably. )
4. Relationship among bandwidth, bit width and bus clock
Bus bandwidth = bus bit width × bus clock
For example, the PCI bus bit width is 32 bits, and the bus clock frequency is 33MHz；; Then the bandwidth of PCI bus =32 bit×33MHz/8= 132 MB/s (except 8, bits are converted into bytes, 1 Byte=8 bit).
Second, the bus function
According to the function of the bus (the content of transmitting information), there are three types of buses in the computer, namely, the data bus for transmitting data information, the address bus for transmitting address information and the control bus for transmitting various control information.
1. data bus
Data bus is a bus that transmits data information (various instruction data information) between CPU and memory and between CPU and I/O interface devices. These signals are transmitted back and forth between CPU and memory and between CPU and I/O interface devices through the data bus, so the information on the data bus is transmitted in both directions.
2. Address bus
Address bus transmits the address information sent by CPU to memory and I/O interface devices, and addressing ability is a unique function of CPU. The address information transmitted on the address bus is only sent by the CPU, so the information on the address bus is transmitted in one direction.
3. Control bus
The control bus transmits various control signals, including control signals from CPU to memory and I/O interface devices, and response signals and request signals sent to CPU through I/O interface. Therefore, the information on the control bus is transmitted in both directions. Control signals include timing signals, status signals and command signals (such as read-write signals, busy signals and interrupt signals).
For example, writing data into the memory is carried out through the memory bus (including data bus, address bus and control bus), and data information needs to be transmitted to the memory through the data bus. The unit of writing these data information into the memory must be determined by sending address information to the address bus, and when to start writing data into the memory is determined by the control signal obtained from the control bus.
1 4030301a1is the logical block diagram of the 64-word1bit static memory C850. When writing (or reading) data to a certain unit of the memory, the address information needs to be transmitted to the address bus consisting of A0, A 1, A2, A3, A4 and A5 at first. Second, the chip selection control signal needs to be sent to the CE terminal to make the memory chip in working state; Thirdly, it is necessary to send a read-write control signal at the R/W terminal to determine the write (or read) operation; Only in this way can data be written (or read) from the data input terminal Din (or the data output terminal Dout). The above operations transmit information to address lines, control lines and data lines.
Although some special buses also need to transmit data information, address information and control signals, they do not provide data bus, address bus and control bus separately because of their simple structure. For example, USB, a universal serial bus, includes a power line and a ground line. It only provides four connections, and can only transmit data information, address information and control information through serial transmission in a time-sharing manner.
Third, external frequency, main frequency and front-end bus
There is no oscillator in the CPU, but the clock signal is obtained through the external crystal oscillator circuit, thus executing instructions regularly. The clock frequency provided by this external crystal oscillator to CPU is called external frequency. Both internal data transmission and external data transmission bus of CPU are based on this basic working frequency.
Although the CPU does not have its own clock signal generator, there is a clock frequency doubling circuit inside the CPU to improve the actual running frequency of the CPU. The clock frequency doubling circuit increases the system clock signal (i.e., the external frequency of CPU, such as 133MHz) sent from the outside of CPU by a certain scale factor (i.e., frequency doubling) to obtain the actual working frequency of CPU (i.e., the main frequency, i.e., the internal bus frequency of CPU, note 1). So CPU main frequency =CPU external frequency × frequency doubling. For example, the external frequency of PⅢ 733 is 133MHz, the frequency doubling is 5.5, and the actual working (running) frequency of CPU is 733MHz( 133MHz×5.5).
Note 1: CPU internal bus refers to the bus used to transmit data among arithmetic logic unit ALU, controller, decoder, memory management unit, instruction prefetch unit and bus unit in CPU chip.
Another confusing concept is the front-end bus. The front-end bus refers to the channel for transmitting data between the motherboard chipset (Northbridge chip) and the CPU, so it is also called the CPU external bus, and 1403030 1b 2 is the CPU internal bus flow. Before Athlon was released, the operating frequency of the front-end bus was the same as the external frequency. For example, the external frequency of PⅢ 733 is 133MHz, and its front-end bus also works at 133MHz. In this case, the data transmission bandwidth provided by Pⅲ front-end bus is only1064 MB/s (64 bit×133 MHz/8), which can't meet the data transmission requirements of high-frequency CPU (the theoretical data transmission bandwidth of CPU internal bus is 32bit×733MHz/8=2932MB/s), so CPU manufacturers are interested in the front-end.
After the release of AMD Athlon with Alpha EV6 technology, the data transmission bandwidth of its front-end bus is twice that of the processor without EV6 technology at the same working frequency, and the equivalent working frequency of Athlon front-end bus is no longer equal to the external frequency of CPU, but twice that of CPU. The main technical feature of EV6 is that it adopts double pulse edge data transmission technology (Note 2). At the clock frequency of 100MHz, the data transmission bandwidth of the front-end bus is doubled to1.6 GB/s (64 bit× 2×100 MHz/8 =1.6 GB/. Therefore, the working frequencies of the equivalent front-end bus are 200mhz (1.6gb/s ÷ 64bit =1.6gb/s ÷ 8b = 200mhz) and 266mhz (2.1gb/s ÷ 64bit = Intel's P4 processor works at the external frequency of 100MHz. Due to the adoption of four 64-bit wide front-end buses (that is, four-channel front-end buses, the working frequency of each channel is still 100MHz, but the four channels add up to 400MHz), the data transmission bandwidth of the front-end buses is increased to four times. It reaches 3.2 GB/s (64 bit × 4×100 MHz/8 = 3.2 GB/s), so its equivalent front-end bus works at 400MHz(3.2GB/s÷64bit=400MHz).
Therefore, the frequency of the front-end system bus (FSB) that we often talk about now actually refers to the equivalent working frequency of the front-end bus, that is, FSB= the equivalent working frequency of the front-end bus = the bandwidth of the front-end bus ÷ the bit width of the front-end bus, thus distinguishing the frequency of the front-end bus from the original external working frequency (that is, the external frequency of the CPU). In the formula, the bit width of the front-end bus is the bit width of the external data bus of the CPU, and now the mainstream CPU.
Note 2: Bilateral data transmission technology is a technology to improve bus bandwidth. The traditional bus only transmits data on the falling edge (or rising edge) of the bus clock signal, while the double-edge data transmission technology can transmit data on the upper and lower edges of the pulse signal, which doubles the bus bandwidth without increasing the bus bit width and bus clock frequency. At present, many buses in PC adopt bilateral data transmission technology. For example, DDR memory and EV6 bus apply this principle.
In fact, CPU external frequency and front-end bus describe the data transmission between CPU and external, but the description angles are different. The external frequency of CPU is purely from the external clock generator of CPU, while the front-end bus is from the perspective of data transmission speed. CPU relies on frequency doubling circuit to achieve higher actual working frequency. The front-end bus, like the frequency doubling circuit of CPU, relies on advanced technology (EV6 and four-channel front-end bus design) to reach twice or four times the actual working frequency. 1403030 1C 3 is the schematic diagram of data transmission along the line.
For example, 1 working year is divided into 365 days (if 1 year is regarded as 1 second, the frequency of working year is 365Hz, and the period is 1/365 years, that is, 1 day is a cycle), which is arranged by nature and is suitable for everyone. Moreover, every day (that is, within a cycle), everyone's content (equivalent to the instructions executed by the CPU) is different. Ordinary people finish one thing every day, but a person with strong working ability can divide a day into two and a half days, and finish one thing every half day, so he can finish two things a day (equivalent to the dragon processor and the velociraptor processor), and a smart person can add three helpers, so he can finish four things a day (equivalent to the P4 processor). What we see is that the time has not changed, just like a day, that is, the external frequency is fixed, but the workload completed at the same time is different (equivalent to the amount of data transmitted in a unit time), so the actual working efficiency (equivalent to the equivalent working frequency of the front-end bus) is different.
In the history of PC development, the amount of data required by CPU and peripherals in different periods is different, so the bus architecture of motherboards in different periods is also different. Starting from 386DX, the data bus bit width of CPU has increased to 32 bits or even 64 bits, and the bus architecture of motherboard is constantly changing.
Fourth, the motherboard bus architecture.
Many devices use the same bus to exchange data, and the signals between them will interfere with each other. Therefore, when designing the motherboard bus, buffers will be added between CPU, system memory, I/O expansion slot and peripheral interface chip (its function is to isolate, shape and delay the transmitted signals), and these buffers will divide a single bus into different levels of buses 1403030 1d 4.
1.CPU bus connects CPU (through address buffer and data buffer) and peripheral chips to realize data access to memory, I/O channels and peripheral interfaces.
2. The system memory bus is used to connect the memory controller and the memory (through the buffer) to realize data access to the memory.
3. The I/O channel bus (also called expansion bus) is connected with various expansion cards on the I/O expansion slot, and the CPU and system memory exchange data with various expansion cards through the I/O channel bus. In order to make the boards produced by various manufacturers compatible, I/O channel bus must have a unified standard. The data bus and address bus of different I/O channel buses have different bit widths and different working frequencies.
4. The peripheral interface bus is the bus connecting the peripheral interface controller and the keyboard controller on the motherboard. The chips connected to the peripheral interface bus mainly include interrupt controller, DMA controller, timer/counter, parallel interface, keyboard interface and so on.
Verb (abbreviation of verb) ISA bus
ISA industrial standard bus is a 16-bit system bus standard formulATed by IBM in 1984 for introducing PC/AT machines, so it is also called at bus 1403030 1d 4. ISA bus slot * * * has 98 pins and the data transmission rate is 8MB/s, but now the motherboard has gradually cancelled its support for ISA bus. For example, motherboards of 8 10 and 8 15EP generally have no ISA slots (1403030 1e 5 is an enlarged view of the motherboard ISA interface).
Intransitive verb PCI bus
PCI bus is a local bus that is not connected to a specific processor. Structurally speaking, PCI is the main bus inserted between CPU and peripherals. The CPU bus and the PCI bus are connected by a bridge circuit, and high-speed devices such as graphics controller, IDE device, SCSI device and network controller can be connected to the PCI bus (1403030 1f 6 is the overall architecture of the PCI bus motherboard).
The working clock frequency of PCI bus is 33MHz, the bit width is 32 bits (which can be extended to 64 bits), and the bandwidth reaches 133MB/s, which can support multiple groups of peripheral devices at the same time and maintain high performance at high clock frequency. PCI bus supports bus master control technology, allowing intelligent devices to gain bus control when needed (1403030 1g 7 is an enlarged view of PCI interface of motherboard).
With the development of technology, the traditional 32-bit 33MHz PCI bus can no longer meet the data transmission requirements of all devices in the system, even the improved 64-bit 66MHz PCI-X bus (bandwidth is 533MB/s) used in servers and high-end computer systems can not meet the current needs. Therefore, the motherboard chipset factory has reformed the overall architecture of the motherboard, mainly with the following transformation schemes:
1. Increase the bandwidth of system memory bus and front-end bus.
2. Give the original PCI bus to the South Bridge chip for management, and the South Bridge chip is only used to connect the devices on the PCI expansion slot.
3. Increase the bandwidth of the bridge bus (original PCI bus) between the south bridge and the north bridge.
4. The display interface that needs a lot of data is separated from the original PCI bus in the form of AGP bus and hung on the North Bridge chip to provide data for the graphics card independently.
Seven, AGP bus
AGP (Accelerated Graphics Port) is a bus specification aimed at increasing video bandwidth, which first appeared in 440LX chipset. In the system adopting AGP, the graphics card is connected with the main memory through the AGP bus and chipset, and the display data in the main memory can be directly read, which improves the data transmission speed between the display chip and the main memory, reduces the load of the PCI bus, and is beneficial to other PCI devices to exert their full performance (1403030 1g 7 is an enlarged view of the AGP interface of the motherboard).
The development of AGP buses has gone through the stages of AGP 1×, 2×, 4× and 8×. The working clock frequency of AGP bus is 66MHz and the bit width is 32 bits. 1× mode bandwidth is 266 MB/s (66 MHz× 32 bit/8); 2× mode adopts double pulse edge data transmission technology, which can transmit data twice every clock cycle, and the bandwidth is increased to 533 MB/s (2× 66 MHz× 32 bit/8). 4× and 8× modes transmit data four times and eight times per clock cycle (which is equivalent to increasing the working frequency of AGP bus), and the bandwidth is increased to 1 GB/s(4×66MHz×32bit/8) and 2. 1GB/s(8×66MHz×32bit/8) respectively.
AGP 8× is a new graphics port specification issued by Intel, which has been supported by major global graphics card chip suppliers and graphics card manufacturers such as ATi, NVIDIA and Matrox. AGP8X needs memory to provide a large amount of data, which is mainly used in Pentium 4 system, because Pentium 4 motherboard supports Rambus or DDR high-speed memory, and the memory bus can provide 3.2GB/s bandwidth, which can maximize the performance of AGP8X.
Eight. Bridge Bus of South and North Bridges
The PCI bus between the north bridge and the south bridge of the traditional 586 motherboard provides data for PCI cards (graphics cards, sound cards, etc.). ) PCI slots and peripherals connected under the South Bridge chip. Although in the future development, the display interface that needs a lot of data will be independent of the original PCI bus in the form of AGP bus, the traditional PCI bus with only 133MB/s data transmission bandwidth can no longer meet the needs of a large number of peripheral applications with increasing speed and data volume. Therefore, in recent years, various motherboard chipset manufacturers have handed over the original PCI bus to the South Bridge Chip for management, and transformed the bridge bus between the South Bridge and the North Bridge with different schemes.
The solution adopted by Intel is called "Hub Link", which was first used in the i8 10 chipset (and most of its subsequent i8xx chipsets also adopted this architecture). An 8-bit wide bus with a clock frequency of 133 MHz is used between the original North Bridge chip and the original South Bridge chip, and the data bandwidth is 266 MB/s (2× 65,438+0.33 MHz× 8 bit/8). The original PCI bus is connected to ICH (Input/Output Controller Hub), thus improving the data transmission bandwidth between the South Bridge and the North Bridge (1403030 1H 8 is the i845 chipset architecture).
The solution adopted by VIA is called "V-Link", which first appeared in the chipset of VIA Apollo Pro266. Through V-Link technology, the clock frequency of the original PCI bus is increased from 33MHz to 66MHz, and the bandwidth between the north and south bridges is increased to 266MB/s(66MHz×32bit/8). At the same time, the bridge-crossing chip management of PCI bus is original (1403030 1i 9 is Apollo Pro266A chipset architecture).
The scheme adopted by SiS is called "Multithread I/O Link" (MuTIOL for short), which first appeared in its SiS 635 chipset. MuTIOL technology has prepared eight channels with a bit width of 32 bits and a clock frequency of 33.3MHz for peripherals, with a total bandwidth exceeding1GB/s. ..
AMD's proposal is called Hyper Transport Bus, which has been supported by many famous manufacturers such as NVIDIA and Ali. It first appeared in NVIDIA's nForce chipset. At present, its bandwidth has reached 12.8 GB/s, which is 96 times that of the traditional PCI bus. The working clock frequency of Hyper Transport bus is 400MHz, and the maximum bandwidth can reach 800MB/s by using double pulse edge data transmission technology. The advantage of hypertransport bus lies not only in its speed, but also in its "flexible data bandwidth" and other characteristics. A 32-bit bus can transmit several groups of non-32-bit (4 bytes) data at the same time, which speeds up the operation efficiency of the whole system. In the new generation chipset supporting AMD CPU, support for Hyper Transport bus has been added.