Audio signal acquisition
TI DSP chip TMS320V
C5402 has a unique 6-bus Harvard structure, which enables it to work with 6 pipelines at the same time, and the working frequency reaches 100MHz. Two multi-channel buffer serial ports (McBSP0 and McBSP 1) of VC5402 are used to realize seamless connection with AIC23. The multi-channel buffered serial port of VC5402 adds a 2K buffer on the basis of the standard serial port. Every time the serial port sends data, the CPU automatically sends the data in the sending buffer; When receiving data, the CPU automatically writes the received data into the receiving cache. In the automatic buffer mode, it is not necessary to send an interrupt every time a word is sent, but only when it passes through the boundary of the buffer will it generate an interrupt to the CPU, thus reducing the impact of frequent interrupts on the CPU.
The audio chip adopts the high-performance stereo audio A/D and D/A amplifier circuit TLV320 AIC23 of TI company. The chip is highly integrated with analog-to-digital conversion and digital-to-analog conversion components of AIC23, and adopts advanced oversampling technology. The external hardware interface of AIC23 is divided into analog port and digital port. The analog port is used to input and output audio signals, supporting line input and microphone input; There are two sets of digital interfaces, one is a digital control interface composed of /cs, SDIN, SCLK and MODE. AIC23 is a programmable audio chip. The control word of the chip is written into the internal register of AIC23 through the digital control port, such as sampling rate setting and working mode setting. * * * There are 12 registers. The communication between audio control port and DSP is mainly realized through multi-channel buffered serial port McBSP 1.
AIC23 communicates with McBSP0 of DSP through digital audio port. DSP is the master and AIC23 is the slave. The host provides a transmission clock signal BCLKX0 and a transmission frame synchronization signal BFSX0. In this working mode, the received time signal BCLKR0 and the received frame synchronization signal BFSR0 are actually provided by the host. Figure 1 shows the interface connection between AIC23 and VC5402.
The digital audio interface of AIC23 supports both S (Universal Audio Format) mode and DSP mode (specially connected with TIDSP mode), and the DSP mode is adopted here. When working in DSP mode, its frame width can be one bit long.
Fig. 2 is a detailed circuit diagram of audio signal acquisition.
Circuit design and wiring are very important links in the process of signal acquisition, and its effect is directly related to the quality of signal processing in the later stage. For DSP high-speed devices, the external crystal oscillator can reach hundreds of megabytes after internal PLL frequency multiplication. This requires that the signal lines should be of equal length and multi-layer circuit boards should be drawn to eliminate electromagnetic interference and signal reflection. On the premise of two-layer board, the principle of crossing the top and bottom layers, widening the width of power line and ground wire as much as possible, and separating the branch of power line and analog area from digital area can be adopted, which can achieve better results.
Realization of audio AGC algorithm
AGC algorithm
AGC- automatic gain control is a control method that makes the gain of amplifier circuit automatically adjust with the change of signal strength. Realizing AGC can be a hardware circuit, that is, an AGC closed-loop electronic circuit, or a software algorithm. This paper mainly discusses the realization of automatic gain control of audio signal by software algorithm.
Audio AGC is an audio automatic gain control algorithm, more precisely, a peak automatic gain control algorithm, and a mechanism for automatically and dynamically adjusting the gain according to the input audio signal level. When the volume (whether collected or reproduced) exceeds a certain threshold, the signal will be limited. Limiting means that the output of audio equipment no longer changes with the input, but essentially the output becomes a horizontal line at the maximum volume position; When it is detected that the audio gain reaches a certain threshold, the gain will be automatically reduced to avoid clipping. On the other hand, if the collected volume is too low, the system will automatically increase the gain. Of course, the adjustment of the gain will not make the volume exceed the value set by the user in the adjustment wizard. Fig. 3 is a block diagram of an audio AGC algorithm.
Implementation process of AGC algorithm
Firstly, audio data is obtained from the serial port, which is an integer of 16 bits. Generally speaking, these figures are relatively small. The input audio data is projected in a fixed interval by AGC algorithm, so that no matter what the input data points are, they will be mapped to this space in equal proportion. On the one hand, the maximum value of audio data is compared with the original peak value, and if a new peak value appears, a new gain coefficient is calculated; On the other hand, a new peak is obtained in a certain period of time, which has detection performance, and then compared with the original peak, and then a new gain coefficient is calculated. This gain coefficient is relatively stable. When the volume increases, the signal peak will automatically increase, so the gain coefficient will automatically decrease; When the volume decreases, the new peak will decrease and replace the original peak, so that the peak will decrease and the gain coefficient will increase. Finally, the output data is multiplied by the new gain coefficient and mapped to the projection interval of the audio signal input.
Fig. 4 is a program flow chart of an AGC algorithm for audio signals.
AGC_Coff is the initial gain coefficient, and the initial value is1; MaxAGC_in is the gain peak with an initial value of 0; Time is sampling points, and the threshold is 4096; AGC_in is the new audio data, and MAXArrIn is the new audio gain peak; Mapping interval-20000,20000.
The software part of the whole system is a five-person module. The system main function main (), CMD file, interrupt vector table, DSP5402 header file and library function rtdx.lib specially developed for C language. The main function part is the core, which mainly includes: DSP device initialization, MCBSP 1 initialization, MCBSP0 initialization, AIC23 initialization (internal 12 programmable register setting) and algorithm program.
In the integrated development environment of CCS2.0, *. C language and *. Adopt asm language.
Combinatorial programming. Compile and link the written program *. c，*。 Asm and linker *. Cmd to generate the execution target file *. Out, download the execution target file *. Output to the system board through the emulator, debug, compile and run, and input music as an audio signal source to the system board.