Pin arrangement in DS 1302, where Vcc 1 is the standby power supply and VCC2 is the main power supply. When the main power supply is turned off, the clock can continue to run. DS 1302 is powered by the greater of Vcc 1 or Vcc2. When Vcc2 is greater than Vcc 1+0.2V, Vcc2 supplies power to DS 1302. When Vcc2 is less than Vcc 1, DS 1302 is powered by Vcc 1. X 1 and X2 are oscillation sources, and the external crystal oscillator is 32.768kHz. RST reset/chip line selection, all data transmission starts by setting the RST input drive to high level. The rst input has two functions: first, RST turns on the control logic and allows the address/command sequence to be sent into the shift register; Secondly, RST provides a method to terminate single-byte or multi-byte data transmission. When RST is high, all data transmission is initialized, allowing operation on DS 1302. If RST is set to low level during transmission, data transmission will be terminated and I/O pin will become high impedance state. During the power-on operation, RST must be kept low until Vcc≥2.5V. RST can only be set to high level when SCLK is low level. I/O is a serial data input and output terminal (bidirectional), which will be described in detail later. SCLK is always involved.