If (B(2 down to 0) = \"000\"), thenReg3 & lt= reg 1" />
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On the shift operation and multiplication operation in ALU in VHDL?
The problem of displacement is accomplished by connecting lines.

Like 5.

When "100 1" = >

If (B(2 down to 0) = "000"), then

Reg3 & lt= reg 1;

other

Reg 3 < = reg1((7-conv _ integer (b)) drops to 0); Reg 1(7 downto(8-conv _ integer (b)));

endif

No tmp, just delete it.

When there is a shift, b can be covered with only 3 bits.

I didn't make it up. If you have any questions about compilation, keep asking me.