JEDEC minimum standard is the minimum industrial standard for the maximum rated range and static parameters of CMOS integrated circuits, which is formulated under the auspices of Electronic Industry Association (EIA) and Electronic Device Engineering Committee (JEDEC). The following table shows the maximum rated range of CMOS integrated circuits made by JEDEC:

Power supply voltage VDD~VSS 18 ~ -0.5 volts (DC)

The Dc input current IIN is 10 milliampere (DC)

Input voltage VI VSS ≤VI ≤ VDD+0.5 V(DC)

Equipment power consumption PD 200 mw

The working temperature range is T -55~ 125 (ceramic seal) and -40~85℃ (plastic seal).

In the storage temperature range of TSTG -65 ~ 150℃, the input terminals of all CMOS circuits cannot float, so it is best to use a pull-up or pull-down resistor to protect the device from damage.

In some applications, the input terminal should be connected in series with a resistor to limit the current flowing through the protection diode to 10mA.

The rise and fall time of input pulse signal must be less than 15us, otherwise it must be shaped by Schmidt circuit before input into CMOS switch circuit.

Avoid CMOS circuits directly driving bipolar transistors, otherwise the power consumption of CMOS circuits may exceed the specification value.

Because the output impedance of CMOS buffer or high current driver is low, when using large load capacitance (≥500PF), we must pay attention to the situation that these circuits are equivalent to output short circuit.

The output of CMOS circuit cannot be connected in parallel to the line logic state. Because the low output impedance of PMOS transistor and NMOS transistor will short-circuit the power supply.