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Frequency division process of VHDL
Scan is defined as 18-bit vector where it is circled in red. The first green position indicates that when the reset signal comes or the fpga is powered on, the scan will be cleared for the next count. The second green place indicates that each clock is plus 1. The last green place indicates that the upper two bits of scan are allocated to scan_clk, which is the core of the program and outputs two clock signals. Scan_clk( 1) outputs the frequency division of 2 to the power of 18, and scan_clk(0) represents the frequency division of 2 to the power of 17. This process realizes the output of two frequencies at a time.