2-pin: counting output pin? Q 1 .

3-pin: counting output pin? Q0 .

4-pin: counting output pin? Q2 .

5-pin: counting output pin? Q6 .

6-pin: counting output pin? Q7 .

7-pin: counting output pin? Q3 .

8-pin: power ground pin GND.

9-pin: counting output pin? Q8 .

10 pin: the counting output pin Q4.

1 1 pin: the counting output pin Q9.

12 Pin: Counting Carry Pin Company

Pin 13: clock signal input pin CP 1.

Pin 14: clock signal input pin CP2.

15 pin: the count reset pin RST.

16 pin: positive input pin VCC of power supply.

Decimal counter/frequency divider CD40 17 consists of a counter and a decoder, which outputs distribution pulse signals through decoding. The whole output sequence is Q0, Q 1, Q2, ..., Q9, and the high level synchronized with the clock appears in sequence, and the width is equal to the clock period.

CD40 17 has 10 outputs (Q0 ~ Q9) and 1 carry output Q5-9 (pin 12). For every input 10 count pulse, O5-9 (pin 12) can get 1 0 carry positive pulse, and the carry output signal can be used as the clock signal of the next stage.

CD40 17 has three input terminals (MR, CP0 and ~CP 1), and MR is the clear terminal. When the level or positive pulse is applied to MR terminal, its output Q0 is high, and the other output terminals (Q 1 ~ Q9) are low.

CP0 (pin 14) and ~ CP 1 (pin 13) are two clock inputs. If the rising is used for counting, the signal is input from CP0. To count by falling edge, the signal is input from ~ cp1terminal. Two clock input terminals are arranged, which is convenient to cascade and can drive more diodes to emit light.

It can be seen that when CD40 17 has continuous pulse input, its corresponding output ends turn to high level in turn, so it can be directly used as a sequential pulse generator.

Extended data

Decimal counter/pulse distributor CD40 17 is a decimal counter with 10? Decoding output, CP0, CP 1, RST input.

The Schmitt trigger at the clock input has the function of pulse shaping, and there is no limit on the rising and falling time of the input clock pulse. RST？ When the level is low, the counter counts at the rising edge of the clock; Conversely, the counting function is invalid. RST？ When it is high, the counter is cleared.

Johnson? Counter, providing fast operation, 2? Input decoding strobe and burr-free decoding output. Locking the door ensures the correct counting order. The decoded output is usually low level, and remains high level only during the corresponding clock cycle. Every 10? Clock input period CO? This signal completes one carry and is used as the down-pulsating clock of multi-stage counting chain.

Baidu Encyclopedia -CD40 17