Program-controlled digital filter consists of MC 14490 circuit and program-controlled frequency divider, and its input signal comes from the shaping circuit of counter. MC 14490 is a circuit produced by Motorola to eliminate signal jitter. * * * There are six groups of inputs and outputs, and each group has a 4-bit register (integrator) and a logic unit for comparing the input with the contents of the shift register. The shift register shifts the input signal to each bit of the register through a series of timing pulses. The timing pulse can be generated by an on-chip oscillator (see figure 1) or by an external clock circuit and input through the oscillator input.

The basic working principle of the filter is as follows: when the timing pulse arrives, if the current state of the input signal is consistent with the previous state of the register, the state of each bit of the shift register will be shifted back by one bit, so that if the input state is unchanged for four consecutive timing pulse periods, the state of each bit of the shift register will be the same, and finally the signal will be output through the inverter; If the input state changes during this period, each bit of the shift register will return to the original register output state, and the above process will start again. The time domain variable between the input and output signals depends on the jitter characteristics of the input signal edge and the frequency of the clock signal. Therefore, in order to obtain jitter-free output signal, the clock frequency needs to meet a condition: the input signal cannot be changed within four consecutive clock pulse periods. Therefore, changing the frequency of the clock signal input by the oscillator input will change the cutoff frequency of the low-pass filter of the de-jitter circuit. In addition, there is a program-controlled frequency divider in the counter, and its output is connected to the oscillator input of MC 14490. Program-controlled frequency divider can be controlled by CPU, thus realizing program-controlled low-pass filtering.

Fig. 2 is a timing diagram of the filter operation. It is assumed that when all bits of the shift register are input at low level, the signal is finally output at high level; Otherwise, the output signal is low. At the falling edge of the clock pulse 1, the input signal reaches the low level, and the high level is input to the first bit of the shift register. When the falling edge of the pulse passes, the input signal becomes high level again, which causes all bits of the shift register to be reset to low level, so the time series starts again. Between the rising edges of clock pulses 3 to 6, the input signal remains low, so the high level is transmitted to all four bits of the shift register, and the output becomes low at the rising edge of the next clock pulse. After N+ 1 clock pulses, the input jitter is low, and all bits of the register are set to high potential; When N+2 pulses arrive, the state remains unchanged, because the input and output are all low level, and each bit of the shift register is high level; After N+3 pulses, the input signal is a clear high-level signal; On the rising edge of the N+6 pulse, the output goes high because the four low levels are shifted into the shift register.