First of all, without explaining the application of PLL, the internal soft core implementation is directly called without any code involved. As for the frequency division code, I simply write an 8-frequency division code, and everything else is similar.

Module div_8(clk_ 100M, rst, clk _125m);

Enter clk_ 100M, rst.

Output register clk _125m; //8 frequency division output 12.5M

reg[3:0]temp；

Always @ (posedgclk _100m or negedgrst)

begin

If (! rst)

begin

temp & lt= 4 ' b0000

clk _ 125m & lt； = 1 ' B0；

end

else if(temp==4'd3)

begin

clk _ 125m & lt； = ~ clk _ 125m；

temp & lt= 4 ' b0000

end

other

temp & lt= temp+ 1 ' b 1；

end

Terminal module

This is only an 8-frequency division code, and other 16 frequency divisions can be written with reference to this, and the principle is the same.