CMOS inverter
CMOS inverter circuit consists of two enhanced MOS field effect transistors, in which V 1 is NMOS transistor and V2 is PMOS transistor and load transistor.
The gate-source turn-on voltage UTN of NMOS transistor is positive, and the gate-source turn-on voltage of PMOS transistor is negative, and its numerical range is between 2~5V.
In order to make the circuit work normally, the power supply voltage UDD >；; (UTN+|UTP|).UDD can work between 3~ 18V and has a wide range of applications. Working principle: when UI=UIL=0V, UGS 1=0, so the tube V 1 is off, at this time | UGS2 | & gt|UTP|, so V2 is on, and the on-resistance is very low, so UO=UOH≈UDD, that is, the output is high.
When UI=UIH=UDD, ugs1= udd > UTN, V 1 on, and ugs2 = 0.
The main feature of CMOS inverter is that in the AB section, due to the high impedance caused by V 1 cutoff, the leakage current flowing through V 1 and V2 is almost zero.
In the CD segment V2, the impedance is very high, so the leakage current flowing through V 1 and V2 is almost zero.
Only in the BC section, when both V 1 and V2 are turned on, the current iD flows through V 1 and V2, and the iD is the largest near UI= 1/2UDD.