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A detailed description of the book catalogue 100 written in VHDL language.
Introduction -asic design and vhdl language (preface)

Asic design faces severe challenges.

The emergence and development of hardware description language vhdl ii

Characteristics of VHDL language

Advanced synthesis of iv vhdl language

Mixed-level simulation of v vhdl language

Talent—— An Advanced vi vhdl Language Integration System

Vii vhdl language/kloc-the selection of 0/00 cases and the writing goal of this book.

Case 1 Adder with Control Port

Example 2 Adder without Control Port

Example 3 Multiplier

The fourth case comparator

Example 5 Bidirectional Selector

Example 6 register

Case 7 Shift Register

Case 8 Comprehensive Cell Bank

Case 9 Seven-valued Logic and Basic Data Types

10 Case function

Case 1 1 seven-valued logic line or analytic function

Case 12: transfer function

Left shift function in case 13

Case 14 seven-valued logic package

Case 15 Four-input Multiplexer

Case 16 Target Selector

17 parity checker

Case 18 Drawing Unit Library and Its Application Example

Case 19 Cyclic Boundary Consistency Test

The twentieth case protects reserved words.

Case 2 1 process deadlock

22 cases of oscillation and deadlock

23rd oscillation circuit

Case 24 Identification Signal and Identification Function

25th example of signal driven source

Example 26 Attribute Transactions and Parsing Signals

Case 27 Block Protection and Attribute Events, Stability

The 28th Test of Formal Parameter Attribute

The 29th Case of Procedure and Concurrent Statement

Thirtieth case of signal transmission and reception

Modeling of priority mechanism of interrupt handling in case 3 1

The 32nd case of process definition

33rd bit integer comparator and its test.

The 34th Reading and Writing of Data Bus

The 35th example of bus-based data channel

36 data channels based on multiplexer

The 37th Case of Four-valued Logic Function

Case 38 Bitwise OR Operation of Four-valued Logic Vector

The 39th example generates a statement describing the rule structure.

Description of Universal 40th Generation Decoder

Case 4 1 Universal Test Platform

Mixed description of behavior and structure in the 42 nd case

The 43rd Case Four-shift Bit Register

The 44th register/counter

The 45th Case of Sequential Procedure Call

The Use of Universal Default Value in the 46th Example of vhdl Language

The 47th simulation without input components.

The 48th Test Excitation Vector Compilation

Interpretation of the 49th Case of delta Delay

Analysis of inertia delay in the 50th case

Case 5 1: transmission delay drive is preferred.

52nd Multi (Sub) Frequency Divider

The 53rd Case of Three-digit Counter and Test Platform

Description of the behavior of the 54th minute and second count display.

55th address counter

56th instruction read-ahead counter

Example 57 Decoding and Operation of Addition, Subtraction and Multiplication Instructions

58th Example 2-4 Decoder Structure Description

Behavior Description of the 59th Example 2-4 Decoder

The 60th Case of Application of Transformation Function in Part Drawing

Case 6 1: Assignment Compatibility of Two Analytic Types Based on the Same Basic Type

Calculation of the greatest common divisor in the 62nd case

The 63rd Case of Maximum Common Factor Seven-segment Display Coding

The 64th traffic light controller

The 65th Case of Finite State Automata in Air Conditioning System

The 66th fir filter

The 67th Fifth-order Elliptic Filter

Controller of the 68th alarm clock system

Decoder of the 69th alarm clock system

Shift register of the 70th alarm clock system

7 1 alarm clock register and time counter of alarm clock system

Display driver of the 72nd alarm clock system

Frequency divider of the 73rd alarm clock system

The whole assembly of the alarm clock system in the 74th case.

Memory of the 75th case

The 76th case of motor speed controller

The 77th case of neuron computer

Case 78: alu input of am290 1 four-bit microprocessor.

Case 79: alu of AM 29014-bit microprocessor

Case 80 am290 1 four-bit microprocessor ram

Four-bit microprocessor case 8 1 am290 1 register

Output and shift of am290 1 four-bit microprocessor in the 82nd case.

Case 83: Multiplexer in am29 10 Four-bit Microprogramming Controller

Case 84 Counter/Register in am29 10 Four-Bit Microprogramming Controller

The 85th Example of Four-Bit Microprogramming Controller am29 10 Instruction Counter

Am29 10 Four-Bit Microprogramming Controller Stack: The 86th Case

The 87th instruction decoder of am29 10 four-bit microprogrammed controller

Example 88 Controllable Counter

The 89th Case of Four-Bit Carry Adder

The 90th parallel system (1)- coprocessor to realize the window search algorithm.

Case 9 1 Parallel System for Realizing Window Search Algorithm (2)-Serial Memory

The 92nd parallel system (3) implements the window search algorithm-string memory.

The 93rd parallel system (4) implements the window search algorithm-top controller.

The 94th case mb8690 1 pipeline behavior description constitutes the framework.

The 95th example describes the management of mb8690 1 register file.

The behavior description of alu in the 96th case mb8690 1

Behavior description of the 97th shift instruction

Article 98 Description of Single-cycle Instruction

Description of Article 99 Multi-cycle Instruction

100 MB 8690 1 pipeline behavior model

refer to

Appendix i 100 Case Summary Table

Appendix II vhdl terminology in Chinese and English

Appendix III Instructions for Use of vhdl Simulator of TLLent System

Attached CD: The contents include 100 vhdl description files and vhdl simulator of talent system.