This paper introduces the basic knowledge and principle of online testing.
1 Introduction
1. 1 definition
In-Circuit Test (ICT) is a standard test method to check manufacturing defects and defective components by testing the electrical performance and electrical connection of online components. It mainly checks the open circuit and short circuit of online single components and various circuit networks, and has the characteristics of simple operation and fast and accurate fault location.
The flying needle ICT basically only carries out static test, which has the advantage of no need to do fixture and short program development time.
Needle bed ICT can test the function of analog devices and the logic function of digital devices with high fault coverage, but it takes a long time to make a special needle bed fixture for each single board.
Scope and characteristics of 1.2 ICT
Check the electrical performance of the on-board components and the connection of the circuit network. It can be used for quantitative measurement of resistors, capacitors, inductors, crystal oscillators and other devices, functional testing of diodes, triodes, optocouplers, transformers, relays, operational amplifiers and power supply modules, and functional testing of small and medium-sized integrated circuits, such as all 74 series, memories, common drivers, switches and other ICs.
It finds the defects of manufacturing process and components by directly testing the electrical properties of on-line devices. Component classes can check the out-of-tolerance of component values, failure or damage, program errors of memory classes, etc. For the process class, we can find faults such as solder short circuit, wrong insertion, reverse insertion, missing assembly, pin tilt, virtual welding, PCB short circuit, wire break and so on.
The fault of the test is directly located on specific components, equipment pins and network points, and the fault location is accurate. Fault maintenance does not require more professional knowledge. Automatic testing is controlled by program, which is simple to operate and quick to test. The testing time of single board usually ranges from a few seconds to dozens of seconds.
1。 3 meaning
Online testing is usually the first testing process in production, which can reflect the manufacturing situation in time and is conducive to process improvement and upgrading. ICT test has accurate fault location and convenient maintenance, which can greatly improve production efficiency and reduce maintenance costs. Because of its specific test items, it is one of the important test methods to ensure the quality of modern mass production.
Briefly introduce the theory of ICT testing.
Basic test method of 1
1. 1 analog equipment testing
Test with an operational amplifier. The concept of "virtual land" starting from point "a" includes:
Ix = Iref
∴Rx = Vs/ V0*Rref
Vs and Rref calculate resistance for excitation signal source and instrument respectively. If V0 is measured, Rx can be found.
If Rx to be measured is capacitance and inductance, then Vs AC signal source, Rx is impedance form, and C or L can also be obtained.
1.2 isolation (protection)
The above test method is aimed at independent devices, but in the actual circuit, devices are interconnected and influence each other, so Ix ref must be guarded during the test. Isolation is the basic technology of online testing.
In the upper circuit, due to the parallel connection of R 1 and R2, the equation of Ix ref, Rx = Vs/ V0*Rref is not valid. During the test, as long as G and F are at the same potential, no current flows in R2, and the equation of Ix=Iref and Rx remains unchanged. Grounding the G point, because the F point is virtual ground, and the potentials of the two points are equal, can achieve isolation. In fact, G and F are equipotential through isolated operational amplifiers. ICT tester can provide many isolation points to eliminate the influence of peripheral circuits on the test.
1.2 testing of integrated circuits
For digital integrated circuits, vector testing is adopted. Vector testing is similar to truth table measurement, simulating input vector and measuring output vector, and judging the quality of devices through actual logic function testing.
For example, testing of NAND gates.
For the test of analog IC, the corresponding output can be measured according to the actual functional excitation voltage and current of IC, which can be used as a functional block test.
2 Non-vector test
With the development of modern manufacturing technology and the use of VLSI, it often takes a lot of time to write the vector test program of devices, such as the test program of 80386, and it takes a skilled programmer nearly half a year. With the wide application of SMT devices, the fault phenomenon of device pin open circuit becomes more prominent. For this company's non-vector testing technology, Teradyne introduced MultiScan；; GenRad introduced Xpress non-vector testing technology.
2. 1 DeltaScan analog junction testing technology
DeltaScan uses ESD protection or parasitic diodes in almost all digital equipment pins and most mixed-signal equipment pins to conduct simple DC current test on the independent pin pairs of the equipment under test. When the power of the board is cut off, the equivalent circuit of any two pins on the equipment is shown in the following figure.
1 Add a negative voltage to the ground of pin A, and the current Ia flows through the forward bIas diode of pin A ... Measure the current ia flowing through pin A..
2. Keep the voltage of pin A, apply a higher negative voltage to pin B, and the current Ib flows through the forward bias diode of pin B. Since the * * * from pin A and pin B to ground is shared with the current in the substrate resistance, the current Ia will be reduced.
3 Measure the current Ia flowing through pin A again. If Ia does not change (δ) when a voltage is applied to pin B, there must be a connection problem.
DeltaScan software synthesizes the test results obtained from many possible pin pairs on the equipment, so as to obtain accurate fault diagnosis. Signal pins, power and ground pins, and the substrate all participate in the DeltaScan test, which means that in addition to pin disconnection, DeltaScan can also detect manufacturing faults, such as device missing, reverse insertion and broken bonding wires.
A test similar to GenRad is called Junction Xpress. It also uses the diode characteristics in IC, but the test is realized by measuring the frequency spectrum characteristics (second harmonic) of the diode.
DeltaScan technology has become the first technology without additional fixture hardware.
2.2 Frame Scan Capacitance Coupling Test
FrameScan uses capacitive coupling to detect pin disconnection. Each device has a capacitance probe. When a signal is excited at a certain pin, the capacitance probe picks up the signal. As shown in the figure:
1 Multiplex switch board on the equipment selects the capacitive probe on the equipment.
The analog test board (ATB) in the tester sends AC signals to each tested pin in turn.
3 Capacitance probe collects and buffers the AC signal on the tested pin.
ATB measures the AC signal picked up by the capacitance probe. If the connection between the pin and the circuit board is correct, the signal will be detected; If this pin is disconnected, there will be no signal.
Technologies like GenRad are called Open Xpress. The principle is similar.
This kind of process fixture needs sensors and other hardware, and the test cost is slightly higher.
3 boundary scanning boundary scanning technology
ICT tester requires each circuit node to have at least one test point. However, with the improvement of device integration, the enhancement of functions, the miniaturization of packaging, the increase of SMT components, the use of multilayer boards and the increase of PCB component density, it is difficult to place a probe at each node, which increases the manufacturing cost of test points. At the same time, it is difficult to develop a powerful device test library, and the development cycle is prolonged. Therefore, Joint Testing Organization (JTAG) issued the IEEE1149.1test standard.
Ieee 1 149.5438+0 defines several important features of scanning equipment. Firstly, four (five) pins that make up the test access port (TAP) are defined: TDI, TDO, TCK, TMS, (TRST). Test mode selection (TMS) is used to load control information; Secondly, several different test modes supported by TAP controller are defined, including external test, internal test and running test. Finally, a boundary scan description language is proposed. BSDL language describes the important information of scanning equipment. It defines pins as input, output and bidirectional types, and defines the mode and instruction set of TAP.
Each pin of a device with boundary scanning is connected to a unit of a serial shift register (SSR), which is called a scanning unit. The scanning units are connected together to form a shift register chain to control and detect the pins of the device. Its specific four pins are used to complete the test task.
The scan chains of multiple scanning devices form a continuous boundary register chain through their TAP connections, and the pins of all devices connected to the chain can be controlled and detected by adding TAP signals at the chain head. This virtual contact replaces the physical contact of the needle bed fixture on each pin of the device, and the virtual path replaces the actual physical path, which saves a lot of test pads occupying PCB space and reduces the manufacturing cost of PCB and fixture.
As a test strategy, in the testability design of PCB, special software can be used to analyze circuit points and devices with scanning function, and how to effectively place a limited number of test points without reducing test coverage and reducing test points and pins most economically.
Boundary scan technology solves the difficulty of not adding test points, and more importantly, it provides a simple and fast method to generate test charts. You can use software tools to convert BSDL files into test charts, such as Victory of Teradyne, Basic Scan of GenRad and Scan Path Finder. Solve the difficulty of writing complex test library.
TAP access port can also realize on-system programming or on-board programming of CPLD, FPGA and Flash memory.
4 Nand tree
Nand-Tree is a testability design technology invented by Inter. In our products, 8237 1 chip has only this design. Describing its design structure is a file with a general program *.TR2, which we can convert into a test vector.
Accurate fault location and stable test in ICT test have a lot to do with circuit and PCB design. In principle, we require each circuit node to have a test point. The circuit design should enable the states of each device to be isolated from each other without affecting each other. The design of boundary scan and n and tree should have testability requirements.