Process statement start

Process statements are contained in a structure, and a structure can have multiple process statements, which are parallel and can access the signals defined in the structure or entity. Therefore, process statements are called parallel description statements.

All statements in the statement structure are executed in order.

The start of the process statement is triggered by the sensitive signal indicated in the sensitive signal table after the process.

Communication between processes is transmitted by signals.

The syntax is as follows:

Marking: Process (Sensitive Signal Table)

Variable statement;

begin

A set of consecutive statements;

End process mark;

Marking: marking process.

Sensitive signal table: it is a list used by the process to read all sensitive signals (including ports).

Variable description: it mainly includes data type description and subroutine description of variables.

The process from the beginning to the end is a series of continuous execution statements.

Sensitive signal table

The so-called sensitive signal table is a list used to store sensitive signals. In process statements, sensitive signals refer to those signals that can lead to the execution of process statements after changes. One or more signals can be used in the sensitive signal table. When the value of one or more signals changes, statements in the process will be executed. The sensitive signal table can also be ignored, but there must be other forms of sensitive signal excitation in the program. Such as waiting, waiting, waiting and waiting.

Process start statement

In VHDL language, a process has two working states: waiting and executing. When the signal in the sensitive signal table does not change, the process is in a waiting state; When the signal in the sensitive signal table changes, the process is in the execution state.

Synchronization of procedure statements

Not only can there be multiple processes in the same structure, but also multiple processes in the same structure can be synchronized. In VHDL, the clock signal is usually used to synchronize the process. The specific method is to stimulate several processes in the structure with the same clock signal.

Concurrent signal allocation statement

When the signal assignment statement appears inside the process, it is a sequence description statement. When the signal assignment statement is out of the process of the structure, it will appear as a concurrent statement. They are executed in parallel in the structure. Note: Concurrent signal assignment statements are event-driven, so for concurrent signal assignment statements, only when the assignment symbol "

Conditional signal assignment statement

Grammatical structure:

Target signal

Expression 2 When Condition 2 is not,

Expression 3 when condition 3 is else

...

The expression n- 1

Expression n;

When VHDL language program executes this statement, it is necessary to judge the condition first, and then assign the signal. If the condition is met, the value of the expression before the condition is assigned to the target signal; If the conditions are not met, continue to judge until the last expression. If the previous conditions are not met, the value is unconditionally assigned to the last expression, because the last expression does not need conditions.

Select signal allocation statement

Grammatical structure:

Use expression selection

Target signal

Expression 2 when condition 2 is selected,

...

Expression n when condition n is selected;

This statement needs to judge the condition before assigning the value, and assign the value to the additional condition, otherwise it will continue to judge until the last statement. Choosing an assignment statement requires listing the value of the expression in the condition.

Component instantiation statement

In VHDL, the description of the referenced component or module adopts a component statement, which is used to explain the referenced component or module in the structural description part. This is a component description statement.

Syntax format:

The name of the component referenced by the component.

General parameter description;

Port description;

End assembly;

Referenced Component Name: defines a ready-made entity as a component, which is a designed entity name used to define the component name to be used in the structure.

If you want to pass parameters in the structure, you need to describe generic parameters in the component statement (optional);

The description of the reference component port is a list of designed physical port names;

Component description statement is between architecture and start.

Component instantiation reference

After using componet statement to explain the original to be referenced, in order to embed the referenced component into the higher-level structure description correctly, it is necessary to correctly connect the port signal of the referenced component with the corresponding port signal in the structure, which is the function to be realized by the component instantiation statement.

Grammatical structure:

Label Name: Component Name

Universal mapping (parameter mapping)

Prot map (port mapping);

Among them, tag: is the unique identifier of the component instantiation statement, and the tag name in the structure should be unique.

Generic map statement: its function is to realize the assignment of parameters, so that the parameters of reference components can be flexibly changed to optional.

Prot map: Its function is to correspond the port signal of the referenced component with the actually connected signal, so as to reference the component.

In VHDL, in order to connect the port signal of the reference element with the actual signal in the structure, two mapping methods are usually used:

1. Location mapping method: It means that the writing order of the actual signals in the port mapping statement is consistent with the writing order of the signals described by the ports in the componet statement.

2. Name mapping method: in port mapping, the name of the port signal of the referenced component is assigned to each signal of the instantiated component in the structure.

The writing requirements of name mapping statements are not very strict, just connect the corresponding signals of the mapping, and the order can be reversed.

Generated statement

Normal structure

Some circuit parts are arrays of similar components, which are called regular structures. For example, conventional structures such as random RAM, read-only ROM and shift register are generally described by generating statements.

There are two forms of generating statements: for_generate and if_generate.

For_generate is mainly used to describe rules.

If_generate is mainly used to describe the irregularity of structure at its end, such as the particularity of boundary conditions.

For_generate statement

Tags: for loop variable generation in discrete range

Parallel processing statements;

End label generation;

Label: used as a unique identifier for the for_generate statement; Optional;

Loop variable: its value will change in each loop;

Discrete Range: used to specify the value range of circular variables. The value of the loop variable will start from the leftmost value in the range and increase to the rightmost range, which actually limits the number of loops.

For_generate and for_loop statements are very similar, but they are different. The processing statements in the loop body of the for_loop statement are sequential, while the statements processed in the for_generate statement are processed in parallel and have concurrency.

If_generate statement

Label: If the condition is generated

Parallel processing statements;

End label generation;

If_generate statement is a parallel processing statement, in which else sub-statement is not allowed.