Keywords: caller ID; FSKHT903274HC9046BF535
1 Introduction
Calling number identification (commonly known as caller ID) has become an important function of telephone communication, and it is also essential in many CTI call centers and switches. Caller ID is mainly divided into four categories in the world: Bellcore FsK is mainly used in China, the United States and Canada; ETSI FSK is mainly used in Europe and Taiwan Province Province; JT FSK is mainly used in Japan; DTMF is mainly used in Taiwan Province Province and India. This paper mainly discusses the decoding method of FSK caller ID, and introduces three demodulation methods based on special circuit, phase-locked demodulation and DSP in detail.
2 dedicated circuit demodulation
The mainstream incoming display circuits are MT88E39, MT88E43 and mt88e 45:ht 9032； of Mitel Company. Hortek company; SM8332NPC company; MCl45447 Freescale Company; EM92547A from EMC company. Taking HT9032 as an example, this paper introduces the FSK decoding method, focusing on the application of I-type or on-hook caller ID, which conforms to the specifications of Bell 202 and V.23 HT9032 contains an FSK demodulator in one circuit, and its pins and functions are compatible with MCl45447 of Freescale Company and EM92547A of EMC Company.
The hardware of the circuit is mainly composed of HT9032 and Mega8 single chip microcomputer of Atmel Company. The FSK baseband signal demodulated by HT9032 is sent to the single-chip microcomputer to capture and interrupt, and the signal code rate is 1200b/s, so Mega8 sets the clock frequency to 1.2 kHz to sample and judge the signal. Because the sampling period can not be ideal 1200 Hz, the sampling position will gradually deviate from the symbol center, leading to wrong judgment. Therefore, after each falling edge capture interrupt occurs, the counting clock of the single chip microcomputer is reset to correct its sampling phase. Then delay 0.4 ms(2.4kHz), take the midpoint of the symbol, and start sampling at the rate of 1.2 kHz, and get a bit stream of 0 and 1, which is synthesized into byte information of 10 bit. The start bit of each byte is 1, the end bit is 0, and the middle 8 bits are information. Finally, according to the single data message format recognized by the caller, the required message words are extracted to obtain the date and number of the incoming call.
There are two formats of caller identification information data: single data message format (SDMF) and composite data message format (MDMF). The former is simple and commonly used.
Channel occupancy signal: It consists of a group of 300 consecutive "0" and "1" (binary bits) alternately, with the first bit being "0" and the last bit being "1". In the call state, the channel occupied signal is not sent, and the subsequent signal is considered as a valid signal only after the receiver correctly receives it.
Flag signal: It consists of 180 flag bits (logic "1") (on-hook state) or 80 flag bits (call state), that is, continuous high level.
Message type word: "04H" in single data format, indicating sending calling number information.
Message length word: one byte, which is the number of words in the message.
Message content: The message content in single data message format is as follows: date, time (month, day, hour and minute), ***8 bytes; Calling number (if allowed); If the calling number is not allowed to be displayed, the character "p" is sent; When the terminal switch cannot obtain the host number, the character "0" will be transmitted.
Checksum: The algorithm of checksum is to sum and complement the message data (i.e. message type words, message length words and message data words in a single data format) according to the modulus of 256 to get the checksum.
According to the analysis of single data message format, the incoming call display time is: August 14, 13: 47, the incoming call number is:13386198301,and the parity bit is 0x 12. The sum of all data (including parity bits) is 00 according to the modulus of 256, which proves that the received data is completely correct.
3 PLL demodulation
Phase locked loop mainly includes phase detector, loop filter and voltage controlled oscillator. The phase detector can be divided into digital phase detector and analog phase detector. Digital phase detector is generally composed of XOR gate or edge trigger, analog phase detector is composed of multiplier, and loop filter is generally proportional-integral filter circuit.
α(nT) is the modulated digital signal, and△ω is the frequency offset of FSK signal. Assuming that the bandwidth of PLL is wide enough, the loop is locked, and the frequency of VCO output signal is the same as that of input signal, which is also FM wave. If the phase detector adopts sine phase detector, the VCO output voltage is:
φe is the steady-state phase difference, which is constant, generally less than 90, and inversely proportional to the loop gain. The VCO output frequency can be obtained by equation (2) as follows
The relationship between the output frequency of the voltage-controlled oscillator and the control voltage is ω=ωc+AoVc, which can be obtained by comparison with Equation (3).
It can be seen that the control voltage of the VCO is proportional to the modulation signal of FSK. In the actual circuit, it can be restored to digital signal by adding some shaping comparison circuits to complete the demodulation of FSK.
PCI and PC2 are gate phase detectors and edge triggered phase detectors, respectively. The PCI output is selected here, and the passive proportional-integral filter is used as the loop filter. According to the characteristics of FSK caller ID signal, the parameters of 74HC9046 are set as follows: center frequency fc= 1.7 kHz, tracking bandwidth 2fL= 1.5 kHz, and loop filter bandwidth 1kHz. R 1= 10 kHz, C 1 = 0.3 μ f, R2=∞ (refer to the data sheet of 74HC9046 for specific calculation). Because the error of general capacitor is relatively large, R 1 should be fine-tuned according to the actual situation to ensure that the loop can track FSK signals.
The input signal is replaced by a signal source with the center frequency of 1.7kHz. The frequency offset is plus or minus 0.5 kHz, and the modulation rate is1.2 KB/s. ..
Because the digital phase-locked loop is adopted, the input signal must be TTL, so the input signal should be amplified and limited. The frequency of the limited signal is the same as that of the phase-locked output signal, but there is a little phase difference, that is, the steady-state phase difference. When the PLL enters the locked state, the voltage of its VCO is consistent with the baseband signal. Since the caller ID signal of FSK system 1 stands for 1.2 kHz, and 0 stands for 2.2 kHz, the signal output by phase-locked demodulation will be input to the single chip microcomputer for message word extraction. The processing method of single chip microcomputer is the same as the demodulation method based on special circuit, so I won't repeat it here.
Demodulation based on DSP
There are many software demodulation methods for FSK signals, and differential demodulation is a relatively simple and easy-to-implement method. Its theoretical basis is that the two frequencies of FSK signal are ω 1 and ω2 respectively. Ω = Ω o+Ω, if Ω > o, Ω = Ω 2; If △, ω
The above formula shows that if the input signal is delayed by π/2 or 3π/2 phases, that is, ωoτ=π/2, x (t) =-A2/2 * sin (△ω τ); When ωoτ=3π/2. X (t) = A2/2Sin (△ψ ψ). Bipolar voltage can be obtained to distinguish "0" from "L". The demodulation algorithm block diagram of DSP is shown in Figure 3.
After the algorithm is determined, it is simulated on system view. The input PN sequence rate is 1.2 kb/s, the center frequency of FSK modulator is 1.7 kHz, and the frequency offset is ±0.5 kHz. In order to delay an integer number of sampling points, the sampling rate of DSP is 34 kHz, which is an integer multiple of the central frequency (ωo= 1.7 kHz). Therefore, ω o * τ = π/2 =1.7 (4x34000)-1) = 5 samples, and the cutoff frequency of the low-pass filter is1.2khz.
It is worth noting that when selecting the delay point, when the signal is delayed by π (34,000/1700/2 =10 samples), the signal amplitude obtained is far less than π/2 delay, and the same conclusion can be drawn from Equation (6).
Based on the realizability of simulation, the author adopts BF535 DSP from analog devices. DSP has a main frequency of 300MHz, two 40-bit Macs and two 32-bit ALUs, four 8-bit video processing units and 16 address addressing units. The DSP integrates 308 KB RAM and has rich external interfaces. The delay, filtering, multiplication and message word extraction in the algorithm are more than enough, and the actual code is only ll KB.
5 concluding remarks
The demodulation method based on special circuit is low in cost, practical and simple, reliable in performance, and suitable for the design of small caller ID. Most caller ID products adopt this method.
PLL decoding method is based on hardware FSK demodulation used in most communication demodulation circuits. Its advantage is high sensitivity, especially in the case of low signal-to-noise ratio, but its disadvantage is complex circuit and inconvenient debugging. Moreover, for most digital PLL integrated circuits (such as 74HC9046 or 4046), VCO is greatly affected by temperature when it works at high frequency (>: 6 MHz), so it needs to add a temperature compensation circuit to work normally.
Decoding based on DSP is a pure software demodulation method, which has the advantages of flexible design and convenient modification. However, compared with the special circuit demodulation method, the cost is too high, and the algorithm should be adjusted accordingly in the case of poor signal-to-noise ratio.