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What is the result of addition overflow between integer data in verilog?

For example, if the sum of two 8-bit integers is saved as an 8-bit integer, it will overflow

For example, 128+128, the actual result should be 256 (0x100 in hexadecimal), But because the data has 8 lower bits, the high bits overflow, and the final verilog result is 0 (0x00)