In chipscope, there are usually two ways to set the signal to be captured.

1. Add the cdc file, and then find and add the signal in the netlist.

2. Add IP cores of ICON, ILA and VIO.

The first method, with little code modification, appropriately retains the design level and network name, and the graphical interface is easy to find.

The signal to be captured.

The second method, the code changes greatly, and you need to be familiar with the settings of related IP, which has the advantage of being controllable.

Icon and call VIO.

Similarly, Vivado has two settings.

1. Look for relevant signals in the comprehensive netlist, right-click to open the menu, and then set the mark for debugging.

2. increase the IP core of ILA and VIO.

The first method is very similar to chipscope's first method:

1. Both need to be integrated before setting;

2. Need to reserve a certain design level or network name to facilitate signal search;

3. Not all signals can be captured, and the signals that cannot be captured are displayed as gray and vivado in chipscope.

There is no marked debugging option in the right-click menu;

The second method is more similar. Vivado is compatible with ISE IP and can directly call the phase of chipscope.

Turn off IP, only use Chipscope when debugging, and you can use Vivado's own ILIP design.

But the biggest problem is that Vivado does not provide the IP of ICON for selection, which further buried the status of ICON.

In addition, the early Vivado IP directory provided Chipscope's ICON, ILA and VIO IP cores to choose from. At present, these IPS have been cancelled and only support Vivado's own ILA/VIO IP core.

This is a very simple design code of Vivado logic analyzer.

`Time scale 1 nanosecond/1 nanosecond

Module Nexy_4 (

Input CLK,

Output [3:0] O_ST_COUNTER,

Output O _ time counter _ output

);

Wire clk _100;

Clock _ Wizard _ 0 CLK _ Unit

(

. clk _ in 1(CLK)，

. clk_out 1 (CLK_ 100)，

. Locked ()

);

reg[7:0]startup _ counter = ' B0；

Forever @ (posedgclk _100)

if(startup _ counter = = 8 ' b 1 1 1 1 1 1 1)begin

Start the counter & lt = 8' b00000011;

End or start.

Start counter & lt = startup _ counter+8' b1;

end

end

Assignment o _ st _ counter = startup _ counter [7: 4];

wire[47:0]time counter _ Result _ wire；

reg[47:0]time counter _ Result _ reg = ' B0；

Reg time counter _ output;

Forever @ (posedgclk _100)

Time counter _ result _ registration < = time counter _ result _ wire;

end

Time counter TimeCounter_Unit (

. CLK (CLK_ 100),//input line clk

. A (2'b0 1),//input line [1: 0] A

. C (TimeCounter_Result_reg),//input line [47: 0] C

. P (TimeCounter_Result_wire) // output line [47: 0] P

);

Forever @ (posedgclk _100)

Time counter _ output < = timecounter _ result _ reg [47];

end

assign O _ time counter _ OUTPUT = time counter _ OUTPUT；

Terminal module

The method of selecting the signal to be captured in the comprehensive netlist.

Only signals under the network can set debugging flags.

Very unreasonable in principle. In the capture interface of Chipscope, only the Reg signal can be captured, and Vivado is Net, which is also unreasonable from a practical point of view. LUT can be directly captured, which is not suitable for design in principle and timing.

During setup debugging, the tool will automatically analyze the clock domain of the signal and add the clock. In rare cases, you can modify the clock domain by right-clicking to select it.

Set the storage depth on the next page. Compared with ChipScope, the width of the signal does not need to be set in advance, but is set automatically according to the captured signal. Vivado is really convenient.

After setting, you can modify the properties of ILA core in the properties. Implement after confirmation.

However, it can be seen from the implementation results that although the signal of LUT is captured, the IP of ILA has been isolated by adding a registry. Considering this result, Vivado's ILA design is still excellent.

But even so, it is an incomprehensible explanation that the Reg signal in the netlist cannot be set with mark debug.

Finally, the setting of Vivado logic analyzer will be reflected in XDC file in the form of Tcl script.

After the implementation, the bit file is generated, the hardware manager is opened, the FPGA is downloaded and configured, and the Vivado logic analyzer is used.

1. The interface after downloading the bit file is shown in the following figure.

2. Here is a problem. In Vivado 20 14.2, the debug probe window will not open automatically. You can find this window in the Window menu.

3. The interface after opening the debugging probe window is shown in the following figure.

4. In debugging the probe, you can set the trigger signal by dragging the signal to the basic trigger setting.

5. After setting the trigger signal, you can start to capture the signal.

6. You can set operators, cardinality and values for each group of trigger conditions to set specific trigger conditions, or you can combine multiple trigger conditions.

7. For easy observation, the data in the window data depth is set to 16 data.

8. Capture data again after setting, and you can see that only 16 data are captured at a time.

9. You can set the number of windows. Here, the number of windows is set to 2, representing two windows, and the data captured each time is 4.

10. After re-triggering, you can see that it has been triggered twice, and the triggering conditions are the same each time, that is, startup_counter = 8'h03. As can be seen from the following two counters, it is two consecutive captures.

In fact, similar to chipscope, you can set the conditions for capturing data.

1. Set the capture mode to basic.

2. You can see the interface of basic capture settings under basic trigger settings.

3. As can be seen from the above two figures, the trigger signal is starup_counter, the trigger condition is 03, the capture condition is 88, and the trigger position is 7.

4. According to the capture result diagram, a * * * captured 16 data, and the trigger condition is at the position of the seventh data, so the trigger condition will be captured. In addition, only when the data bit is 88 will the data before and after the trigger condition be captured.

5. Set the trigger position to 0 and recapture. It can be seen that the first data is the trigger condition, and the subsequent data will only be captured in the case of 88.

6. The functions of ChipScope and Vivado logic analyzer are preliminarily compared here.

ChipScope Vivado logic analyzer basic edition

Multiple trigger value support support

Trigger condition combination support

Trigger position selection support

Multi-window trigger support

Repeated trigger support

Conditional capture support

State machine triggering 16 state is not supported.

Counter auxiliary support is not supported.

Flag bit display is not supported. Not supported.

The repetitive trigger function is beyond the scope of this article.

As can be seen from the table, ChipScope seems to be more powerful. Although it is convenient to set up Vivado to capture signals, it seems that it is not as convenient as ChipScope in debugging.

It should be noted that Vivado did not confirm these functions, but they were not provided in the basic functions. The usage of Advancedd DD DD will be introduced in a subsequent blog post.