The EDA tools provided by PLD device manufacturers are well-known, such as Max+plus II of Altera Company, Foundation series Latice Vantis of Quartus II Xilinx Company and ispuats system of Quartus II Xilinx Company.
② The commonly used comprehensive tools of EDA tools provided by third-party professional software companies include FPGA compiler II of Synopsys, LeonardoSpectrum Synplicity of Exemplar Logic, and Synplify, a third-party tool software developed by FPGA manufacturers for CPLD/ software supplement and optimization. For example, Max+plus II and Quartus II are generally considered to be weak in the logical synthesis of VHDL/Verilog HDL. If special HDL tools are used for logic synthesis, the comprehensive quality will be effectively improved.
Development of programmable logic devices
The design of CPLD/FPGA becomes more and more complicated. Using hardware description language to design programmable logic circuits has become the general trend. At present, the most important hardware description languages are VHDL and Verilog HDL, both of which have been confirmed as IEEE standards. The whole process of developing programmable logic circuits with VHDL/Verilog HDL language is as follows.
Any text editor can edit text, but it is usually in a special HDL editing environment, because professional integrated development environment usually provides various structural templates, which can customize the color display of various elements (such as keyword string comments, etc.). ) to improve readability and input efficiency.
② Functional simulation: transfer the file to HDL simulation software for functional simulation, and check whether the logical function is correct.
③ Logic optimization and synthesis: the source file is transferred to logic synthesis software for logic analysis, that is, the high-level description (behavior or data flow level description) is transformed into the low-level netlist output (register and gate level description). The logic synthesis software will generate EDA industry standard files in EDIF (Electronic Design Exchange Format) format. There are two key factors that affect the comprehensive quality in PLD development, namely code quality and software comprehensive performance.
④ Adaptation and Segmentation If the whole design exceeds the macro-cell or I/O cell resources of the device, the design can be divided into multiple devices of the same series.
⑤ Assembly or Layout Wiring Transfer the EDIF file into the software provided by PLD manufacturers for assembly (for CPLD) or layout wiring (for FPGA), that is, write the designed logic into CPLD/FPGA devices.
⑥ Timing simulation, instant delay simulation. Because different devices and different layouts have different effects on the delay, timing simulation is an essential step to test the design performance of the system.
The basic process of PLD design and development using VHDL language is shown in the figure. If the CPLD device of Altera company is selected as the target device, the above process can be completed in the Max+plus II or Quartus II integrated development environment provided by Altera company, but if the special EDA integration tool is selected as a supplement to complete the logic optimization and comprehensive design, the quality of the third-party integrated software will be better. The main function is to logically synthesize the source files of HDL language, generate EDA industry standard files of edf, and then transfer the edf files into the development software provided by PLD manufacturers for compilation and simulator programming, and finally complete the whole design. For Altera's CPLD devices, we choose Quartus II+LeonardoSpectrum's EDA combination development mode. More importantly, the vast number of learning enthusiasts can get it for free on the website. Let's briefly introduce the application of Quartus II software.
Quartus II is the fourth generation integrated development environment for programmable logic devices of Altera Company, which provides all functions from design input to device programming. Quartus II can generate and identify the EDIF netlist file VHDL netlist file and Verilog HDL netlist file, which provides a convenient interface for other EDA tools and can automatically run other EDA tools in Quartus II integrated environment.
The development process of Quartus II software can be summarized as the following steps: design input, design compilation, design timing analysis, design simulation and device programming.
() Design input
Quartus II software provides a new project wizard in the file menu ..... This wizard guides designers to complete the project creation. When designers need to add a new VHDL file to the project, they can choose to add it through the new option.
() Design and compilation
Quartus II compiler has the following functions: checking design errors, comprehensively extracting logic timing information, adapting and dividing the designated Altera series devices, and the output files will be used to design simulation timing analysis and device programming diagrams. Advanced FlowTabs Interface of LeonardoSpectrum Software ① First, make sure that the software is in compilation mode, which can be selected through the processing menu.
② Select the compiler setting item in the processing menu, as shown in the figure, and carry out device selection mode setting synthesis, adaptation option setting, design verification, etc.
(3) Click Start Compiling Item under the Processing menu to start the compilation process.
(4) Check the compilation results as shown in the figure, and we can get a detailed compilation report.
() Design time sequence analysis
Click the Timing Settings … option under the item menu to set the time parameters conveniently. The timing analysis function of Quartus II software will automatically run after the compilation process, and it will be displayed in the timing analysis folder of the compilation report as shown in the figure, in which we can get the setting time tSU pin of the highest frequency fmax input register. The detailed report of time parameters, such as the delay tCO from the pin delay tPD output register clock to the output and the input holding time tH, can clearly determine whether the timing requirements of the system are met.
() Design simulation
Quartus II software allows designers to use a text-based vector file (vec) as the excitation of the simulator, and can also generate a vector waveform file (vwf) as the excitation waveform of the simulator in the waveform editor of Quartus II software. The editing method is similar to MAX+PLUS II software. Select the simulation mode option under the machining menu to enter. Simulation Mode Select Simulator Settings ... Simulation Settings dialog box. Here, you can select the simulation mode of simulation file (functional simulation or time series simulation), and then click Run Simulator to start the simulation process.
() equipment programming
Designers can download the configuration data to the device through MasterBlaster or ByteBlasterMV communication cable, and program the device through passive serial configuration mode or JTAG mode. They can also program multiple devices in JTAG mode. When programming or configuring equipment with Quartus II software, you need to turn on the programmer first (select Open Chai in the new menu option). N Description file) In the programmer, you can set the programming mode (mode drop-down box), configure the hardware (programming hardware dialog box), and select the programming file (Add File … button). Save the above configuration to generate a cdf file, which stores the device name, device design and hardware settings and other programming information. When the above process is correct, click the Start button to start programming the device.
Application of Leo Spectrum Software
LeonardoSpectrum is a professional VHDL/ of Exemplar Logic, a subsidiary of Mentor Graphics. Verilog HDL comprehensive software is easy to use and has strong controllability. You can make comprehensive optimization in LeonardoSpectrum and generate an EDIF file as the compilation input of QuartusII. This software has three logical synthesis methods: synthesis wizard, quick setup and advanced process tab (see detailed process), and the functions completed by these three methods are basically the same. The synthesis wizard method is the simplest, and the advanced FlowTabs method is the most comprehensive. This method has six options, and the following functions are completed as shown in the figure. Device selection, design file input constraints, optimization selection, output netlist file setting, and selection of call layout and routing tools.
Each of the above steps provides corresponding help, simple and clear. It should be noted that when inputting design files, the order of the files should be arranged correctly, with the bottom files in front and the top files in the back, so that LeonardoSpectrum software can establish the database correctly. After the synthesis, the output netlist file (EDF) can be used as the design input of MAX+PLUS II or Quartus II. Then complete the steps of compilation, simulation, time sequence analysis, device programming, etc., and complete the design process of the whole system (a), (b), (c) and (the influence of VHDL coding mode on the comprehensive quality.
VHDL language supports all simulation functions, but not all of them can be integrated. Many hardware descriptions and simulation structures of VHDL programs are not realized by corresponding digital circuits. Some descriptions can be mapped to corresponding digital circuits in theory, but their accuracy cannot be guaranteed, such as delay models. With the improvement of synthesis algorithm technology, the description of RTL(Register Transfer Level) circuit for some register transfer levels can be effectively optimized, but it is not enough for more general circuit description, so whether the synthesis results meet the given time constraints and area constraints depends on VHDL coding method. The following experience is believed to be helpful and enlightening to improve the comprehensive quality.
() Enjoy resources * * *
For example, in the following two codes, (a) only one adder is needed to complete the same function, and (b) only one adder is needed to effectively reduce the use area.
Sometimes * * * sharing of resources can be realized by proper recombination of brackets, such as input signals B and C in the following two codes (C) and (D), and * * * sharing of adders can be realized.
() Use integer with limited range.
In VHDL, the value range of unconstrained integer is ~+,which means that it needs to be represented by at least bits, but usually it will waste resources. Some comprehensive software will automatically optimize them, but it takes considerable time. Therefore, if you don't need the whole range of integer data, it's best to specify the range, for example.
Signal *** all_int: integer range downto.
*** all_int only needs bit instead of bit in this example, which effectively saves the device area.
() Using Macro Modules
When general logic structures such as arithmetic logic and relational logic are used in VHDL, most EDA development software and special comprehensive tools usually contain optimization macro modules for specific processes for us to choose from. These modules can be divided into sequential circuit macro modules, operational circuit macro modules and memory macro modules. They have high execution efficiency, which makes the comprehensive results smaller in area, higher in frequency and shorter in compilation time. Of course, they are technology-specific, which will make VHDL programs depend on specific device families and affect the advanced design optimization of portability (e) and (f).
The above methods are fully optimized without changing their functions. Sometimes we can change their functions slightly and improve the comprehensive efficiency without hindering the constraints of design specifications. Refer to the following two examples (e) and (f).
In (e), the synthesis tool establishes an incremental counter and a complete comparator. In (f), the synthesis tool establishes a down counter and a comparator with a constant of zero. Because the comparison with constants is easier to realize, it takes up less logical units, and (f) the program is more efficient.
In addition, because the synthesis tool can only support a subset of VHDL, in order to ensure the consistency of simulation before and after synthesis, the following statements should be avoided during synthesis.
◇ Avoid using the wait xx ns statement, which will not be integrated into the actual circuit components.
◇ Avoid using after xx ns, and the after statement will be ignored when synthesizing with comprehensive tools.
Avoid assigning initial values when declaring signals and variables, because most synthesis tools ignore initialization statements. If the initialization statement is used, the results of synthesis and simulation will be different.
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