ICT, In-Circuit Test, is a standard testing method to check for manufacturing defects and defective components by testing the electrical properties and electrical connections of online components. It mainly checks the open and short circuit conditions of individual components online and various circuit networks. It has the characteristics of simple operation, fast speed, and accurate fault location.

Flying probe ICT basically only performs static testing. The advantage is that it does not need to make fixtures and the program development time is short.

Bed-of-needle ICT can test analog device functions and digital device logic functions, with high fault coverage. However, a dedicated bed-of-bed fixture is required for each board, and the fixture production and program development cycle is long.

1.2 Scope and Characteristics of ICT

Check the electrical performance of the online components on the finished board and the connection of the circuit network. It can quantitatively measure resistors, capacitors, inductors, crystal oscillators and other devices, perform functional tests on diodes, transistors, photocouplers, transformers, relays, operational amplifiers, power modules, etc., and perform functional tests on small and medium-sized integrated circuits, such as all 74 series, Memory type, common driver type, switching type and other ICs.

It discovers manufacturing process defects and component defects by directly testing the electrical performance of online devices. The component class can detect component value out-of-tolerance, failure or damage, Memory class program errors, etc. For the process type, faults such as solder short circuit, wrong insertion, reverse insertion, missing installation of components, lifted pins, virtual soldering, PCB short circuit, disconnection and other faults can be found.

The tested fault is directly located on the specific component, device pin, and network point, and the fault location is accurate. Repair of faults does not require more professional knowledge. Using program-controlled automated testing, the operation is simple and the test is quick and fast. The test time of a single board is generally from a few seconds to tens of seconds.

1.3 Significance

Online testing is usually the first testing process in production, which can reflect the manufacturing status in a timely manner and is conducive to process improvement and improvement. Faulty boards tested by ICT can greatly improve production efficiency and reduce maintenance costs due to accurate fault location and easy maintenance. Because of its specific test items, it is one of the important testing methods for quality assurance in modern large-scale production.

A brief introduction to ICT testing theory

1 Basic testing method

1.1 Analog device testing

Use operational amplifiers for testing. The concepts of "virtual ground" from point "A" are:

∵Ix = Iref

∴Rx = Vs/ V0*Rref

Vs and Rref respectively Calculate resistance for excitation sources and instruments. After measuring V0, Rx can be calculated.

If Rx to be measured is a capacitor or inductor, then Vs AC signal source and Rx is in the form of impedance, C or L can also be obtained.

1.2 Isolation (Guarding)

The above test method is for independent devices. However, in the actual circuit, the devices are connected to each other and affect each other, so that Ix and ref must be isolated during testing. (Guarding). Isolation is an essential technique for online testing.

In the above circuit, due to the shunt connection of R1 and R2, the equation Ix ref and Rx = Vs/ V0*Rref does not hold. During the test, as long as points G and F are at the same potential and no current flows through R2, Ix=Iref remains, and the equation of Rx remains unchanged. Connect point G to the ground. Since point F is virtual ground and the potential of the two points is equal, isolation can be achieved. In actual practice, G and F are at the same potential through an isolated operational amplifier. The ICT tester can provide many isolation points to eliminate the impact of peripheral circuits on testing.

1.2 Testing of IC

For digital IC, Vector test is used. Vector testing is similar to truth table measurement, stimulating the input vector, measuring the output vector, and judging the quality of the device through actual logic function testing.

For example: NAND gate test

For testing of analog IC, the voltage and current can be stimulated according to the actual function of the IC, and the corresponding output can be measured as a functional block test.

2 Non-vector testing

With the development of modern manufacturing technology and the use of very large-scale integrated circuits, it often takes a lot of time to write vector test programs for devices, such as the test program for 80386 It takes a skilled programmer nearly half a year. The extensive application of SMT devices has made the fault phenomenon of device pin open circuit more prominent. To this end, each company's non-vector testing technology, Teradyne launched MultiScan; GenRad launched Xpress non-vector testing technology.

2.1 DeltaScan analog junction test technology

DeltaScan uses electrostatic discharge protection or parasitic diodes that are found on almost all digital device pins and most mixed-signal device pins to test the A simple DC current test is performed on individual pin pairs of the device. When the power to a certain board is cut off, the equivalent circuit of any two pins on the device is as shown in the figure below.

1 Apply a negative voltage to ground on pin A, and current Ia flows through the forward bias diode of pin A. Measure the current Ia flowing through pin A.

2 Maintain the voltage of pin A, add a higher negative voltage to pin B, and the current Ib flows through the forward bias diode of pin B. Since the current from pin A and pin B to ground is shared with the current in the substrate resistor, the current Ia will decrease.

3 Measure the current Ia flowing through pin A again. If Ia does not change (delta) when voltage is applied to pin B, there must be a connection problem.

DeltaScan software combines test results from many possible pin pairs on the device to produce an accurate fault diagnosis. Signal pins, power and ground pins, and substrates all participate in DeltaScan testing, which means that in addition to pin disconnection, DeltaScan can also detect manufacturing faults such as missing components, reverse plugging, and disconnected bonding wires.

The GenRad-style test is called Junction Xpress. It also uses the characteristics of the diode in the IC, but the test is implemented by measuring the spectral characteristics (second harmonic) of the diode.

DeltaScan technology does not require additional fixture hardware and has become the first recommended technology.

2.2 FrameScan capacitive coupling test

FrameScan uses capacitive coupling to detect the disconnection of pins. There is a capacitive probe on each device, which excites a signal at a certain pin and the capacitive probe picks up the signal. As shown in the figure:

1 The multi-way switch board on the fixture selects the capacitive probe on a certain device.

2 The analog test board (ATB) in the tester sends AC signals to each pin under test in turn.

3 The capacitive probe collects and buffers the AC signal on the pin under test.

4 ATB measures the AC signal picked up by the capacitive probe. If a pin is properly connected to the board, a signal will be detected; if the pin is disconnected, there will be no signal.

GenRad-like technology is called Open Xpress. The principle is similar.

This technical fixture requires sensors and other hardware and is slightly more expensive to test.

3 Boundary-Scan boundary scan technology

ICT tester requires at least one test point for each circuit node. However, as the integration level of devices increases, the functions become stronger and stronger, the packages become smaller and smaller, the number of SMT components increases, the use of multi-layer boards, and the density of PCB board components increases, it is necessary to place a probe at each node. It is very difficult to increase the test points, which increases the manufacturing cost; at the same time, it becomes difficult to develop a test library for powerful devices, and the development cycle is prolonged. To this end, the Joint Test Group (JTAG) promulgated the IEEE1149.1 test standard.

IEEE1149.1 defines several important characteristics of a scanning device. First, the four (five) pins that make up the test access port (TAP) are defined: TDI, TDO, TCK, TMS, (TRST). The test mode selection (TMS) is used to load control information; secondly, the TAP controller is defined Several different test modes are supported, mainly external test (EXTEST), internal test (INTEST), and running test (RUNTEST); finally, the boundary scan language (Boundary Scan Description Language) is proposed. The BSDL language describes important information of the scanned device. It defines pins as input, output, and bidirectional types, and defines the TAP mode and instruction set.

Each pin of a device with boundary scan is connected to a serial shift register (SSR). The units are connected together and are called scanning units. The scanning units are connected together to form a shift register chain, which is used to control and detect the device pins.

Connect the scan chains of multiple scan devices together through their TAPs to form a continuous boundary register chain. Adding the TAP signal to the head of the chain can control and detect the pins of all devices connected to the chain instead of such virtual contacts. The needle bed fixture has physical contact with each pin of the device, replacing actual physical access with virtual access, eliminating a large number of test pads that occupy PCB board space, and reducing the manufacturing costs of PCB and fixtures.

As a This kind of test strategy can use special software to analyze circuit points and devices with scanning functions when designing testability of PCB boards to determine how to effectively place a limited number of test points without reducing test coverage, which is the most economical way. Reduce test points and test pins

Boundary scan technology solves the difficulty of increasing test points. More importantly, it provides a simple and fast method to generate test patterns using software tools. Convert BSDL files into test graphics, such as Teradyne's Victory, GenRad's Basic Scan and Scan Path Finder, to solve the difficulty of writing complex test libraries.

The TAP access port can also be used to implement tests such as CPLD, FPGA, etc. Flash Memoroy's online programming (In-System Program or On Board Program).

4 Nand-Tree

Nand-Tree is a testability design technology invented by Inter Company. Among our products, this design is only found in the 82371 chip. There is a general *.TR2 file describing its design structure. We can convert this file into a test vector.

ICT testing must achieve accurate fault location and stable testing, which has a lot to do with circuit and PCB design. In principle, we require that every circuit network point has a test point. The circuit design should ensure that the status of each device is isolated so that it does not affect each other. The design of boundary scan and Nand-Tree must have testability requirements.