Verilog has four basic values:

0 means logical 0 or "false";

1 stands for logic 1 or "true";

X means unknown;

Z stands for high resistance.

X and z are not case-sensitive here. In other words, 0x 1z and 0X 1Z are the same.

1. 1 integer constant

Integer constants are integers, and Verilog integers have two writing formats:

Decimal number format and radix format.

(1) Decimal number format is a signed number sequence, representing a signed number.

(2) Numbers in radix format are usually unsigned numbers. Its form is as follows:

[Size]' Base value

Size defines the number of digits (length) of the constant, which is optional; Base is the cardinal number, which specifies the decimal system of data, which can be O (octal), B, H, D, and Value is a series, and its form should be consistent with that defined by Base.

7'Hx //7-bit x (extended x), namely xxxxxxx.

4'HZ //4 bit Z, or ZZZZ.

If the length defined by size is greater than the actual length of the number, it is usually added with 0 in the high order of the data sequence. However, if the leftmost bit of this series is X or Z, add X or Z to the left. If the defined length is less than the actual length of the number sequence, the bits beyond the leftmost part of the number sequence will be truncated.

1.2 real constant

In verilog, real numbers are floating-point numbers, and there are two ways to define real numbers:

(1) decimal format, consisting of numbers and decimal points.

(2) Exponential format, consisting of numbers and characters e(E), which must be preceded by numbers and followed by integers:

23_5. 1e2 // Its value is 235 10.0, and the underline is ignored.

3.6E2 // Its value is 360.0.

The e here can be understood as 10.

1.3 string constant

A string constant is a sequence of characters enclosed in a pair of double quotes.

2 variables

2. 1 line network variable

Wire mesh represents the physical connection between components, and it cannot store data. The net is driven, which can be driven by continuous assignment or connecting the output of the component to the net. The assignment component that provides the drive for the network is the "drive source", and the value of the network is determined by the drive source. If no driving source is connected to the wire mesh, the default value of the wire mesh is Z.

Verilog*** has 1 1 wired network type: wire tri wor tri or wand trireg tri0supply 0supply1.

net:net _ kind[msb:LSB]net 1，net2，...，netn

Net_kind is a wire net type; [msb:lsb] defines the highest and lowest bits of the width of the wire net, which is optional and defaults to 1 bit; NetN is the name of the network variable. A net can have multiple driving sources, and each driving source will assign a value to the net. When this happens, the value of the net is determined by the type of the net.

Supplement of bit width;

most significant bit

Refers to the highest value bit in binary. In 16-bit digital audio, 1 bit has the greatest influence on the value of 16-bit word. For example, in decimal number 15389, the number 1 (1) equivalent to tens of thousands has the greatest influence on the numerical value. Compare the opposite least significant bit (LSB). For example, in assembly, the 8-bit binary number 100000 1, where the first 1 is the MSB and the second 1 is the LSB. For example, if it is an integer, the decimal point (there is actually no decimal point, but it is thought that there is a bit between this bit and the next bit) is after LSB, and if it is a decimal point, it is after MSB, where MSB is the sign bit in the signed number.

Among these 1 1 kinds of nets, the first six are often used, and detailed examples are given below.

(1) net and triangle net

Some questions, skip first!

(2) working network and three working networks

Word line or tri-state line or tri-state line

(3) Wonder Net and Trian Net

Wande Line and Trian Line and

(4)trireg network (tri-state register)

This network can store numerical values and can be used to simulate capacitor nodes. When there is no driving source, the default initial value of the tri-state register net is X. When all its driving sources are in high configuration, the value stored in the tri-state register is the last value acting on the net.

(5)tri0 and tri 1 net

Tri 0 tristate 0 tri 1 tristate 1

The characteristics of both are that if there is no driving source (z can be regarded as no driving source), its value is 0(tri0) or 1(tri 1).

(6)supply0 supply 1 network

Power supply 0 is used to simulate "ground", that is, low level.

Power supply 1 is used for analog power supply, that is, high level 1.

2.2 Register variables

A register represents an abstract data storage unit, and the value stored in the register can be changed by an assignment statement. Registers can only be assigned values in always statement and initial statement, which is a powerful structured statement provided by verilog. When unassigned, the default value of the register is x.

Verilog*** has five types of registers: reg integer time real-time real-time.

2.2. 1 register

Type of (1) register

Reg register is the most commonly used register type, which can only store unsigned numbers. If a negative number is stored in reg, it is usually regarded as a positive number.

(2) Declare the memory with reg

Memory cannot be declared directly in verilog. Memory is declared by register array, that is, by reg. It can be said that the memory is composed of several registers, and the size of the memory can be determined by defining the bit width of a single register and the number of registers.

The memory statement is as follows:

reg[msb:LSB]memory 1[upper 1:lower 1]，memory2 [upper2:lower2]， ...............

Msb and lsb define the bit width of a single register of the memory, and memory 1 and memory2 are the memory names; Upper and lower define the sizes of these two memories respectively.

Integer register type

Integer is an integer register and the most commonly used variable type in verilog. This register stores signed integer values. Integers can define a single register or a group of registers. Integer registers can hold at least 32 bits of numbers, but they cannot be accessed as bit vectors.

2.2.3 Time register types

Time type register is used to store and process time, and is usually used in system function $ TERM. Its statement form is as follows:

time time_id 1，time_id2，..........，time _ idN[msb:LSB]；

The msb lsb is a constant that specifies the limit of the range, which will determine the number of time values that can be stored in the register. If no limit is defined and the default value is 1, each register can only store at least 64-bit time values. Registers of time type only store unsigned numbers.

2.2.4 Real and real-time register types

Real (real register) and realtime (real time register) are generally used to store the simulation time in the test module, and their declaration forms are exactly the same. The default value of the real variable is 0, and when the values x and z are assigned to the real register, these values are regarded as 0.

Step 3 show

3. 1 operand

Operands are operands, which are located on the left and right sides of operators. Operands have the following eight types: constant, parameter, net, register, bit selection, partial selection, memory location and function call.

(1) Constant: Constants often appear in expressions and are usually used for operations or assignments. Integer values in expressions can be signed or unsigned. If the integer form in an expression is a decimal integer, it will be regarded as a signed number, and if the integer form is a radix integer, it will be regarded as an unsigned number.

(2) Parameters: parameters are similar to constants, and all parameters in the expression are regarded as constants. Parameter represents a number with an identifier, so it should be assigned a value when defining it.

(3) Network

(4) Registers: Registers are operands with the highest frequency in expressions, and many program statements are designed by converting and transmitting the values stored in registers. Note: Values in integer registers are treated as signed twos complement; The values in real numbers and real-time type registers are treated as signed floating-point numbers; The values in the reg register or the time register are treated as unsigned numbers.

(5) bit selection

(6) partial selection

(7) Memory cells: Memory modeling is to declare register groups with reg, and the assignment of all register cells in memory cannot be completed in one sentence, so memory cells must be assigned. Its form is as follows:

Memory [word address]

Where memory is the memory name and word_address is the number of the cell to be selected. Bit selection or partial selection of memory cells is not allowed.

(8) Function call: The functions in verilog are not much different from those in C language, and they are all used to realize a certain calculation process or complete an event processing. Functions can be called at will, and function calls can also be used as operands in expressions. The called function can be a system function (with the character $) or a user-defined function.

3.2 Operator

Verilog operators are like the following nine types:

arithmetic operator

relational operator

Equality operator

Logical operator

Bitwise operator

Reduction operator

Shift operator

Conditional operator

Join and copy operators

(1) arithmetic operator

+ - * 、 %

Integer division truncates all decimal parts.

The modulo operator looks for the remainder with the same sign as the first operand, such as -7/4, and the result is -3.

If X or Z appears in the operand of an arithmetic operator, the result of the whole arithmetic operation is X. ..

Length of arithmetic operation result

When performing arithmetic operations, the length of operands in the expression may be inconsistent, and the length of the operation result is determined by the longest operand. In the assignment statement, the length of the result of the arithmetic operator is determined by the assignment target length at the left end of the operator.

reg [0:3] Arc，Bar，Crt

reg[0:5]Frx；

arc = Bar+Crt；

frx = Bar+Crt；

In the first assignment, the overflow part of the addition operation is discarded, while in the second assignment, any overflow is stored in the bit Frx[ 1]. In large expressions, the length of the intermediate result should be the length of the maximum operand (this rule also includes the left assignment target when assigning).

Unsigned and signed numbers

When performing arithmetic operation and assignment, we should pay attention to which operands are unsigned and which operands are signed. Unsigned numbers are stored in network, general registers and integers in radix format. Signed numbers are stored in integer registers and decimal integers.

relational operator

Relational operators compare two operands. If the comparison result is true, the result is 1, and if the comparison result is false, the result is 0. Relational operators are usually used with conditional judgments. & gt& lt& gt= & lt=

If x or z appears in the operand, the result is X.

Equality operator

Four kinds: = =! = === ! = = where = = and！ = is a comparison logical value, because some bits in the operand may be X, so the comparison result may also be X. = = = and! = = is a bitwise comparison, so there will be no case where the result is X.

Logical operator

& amp& amp|| !

If the operand is a vector, a non-zero vector is treated as a logic 1.

positional operator

Bitwise operators are logical operations on operands bitwise, such as AND, OR and NOR.

~: unary non&; :binary and |: binary or ~，~ binary XOR or not

Specification operator

The specification operator has only one operand and produces only one result. * * * There are six kinds as follows:

( 1)& amp； The result of AND operation on each bit of the operand.

(2)~ & amp； Conventional and unconventional, conventional and opposite.

(3) The result of the assignment or operation of each bit of the operand.

(4) ~ | Regulations or not

(5) Canonical XOR: If a bit has X or Z, the result is X, and the operand has an even number of 1, then the result is 0; Otherwise it is 1.

Shift operator

& lt& lt& gt& gt

Conditional operator

The conditional operator selects the execution expression according to the value of the conditional expression, and the form is as follows:

cond_expr？ Expression 1: Expression 2

Where con_expr is a conditional expression, and its result is true or false, expr 1 and expr2 are the execution expressions to be selected. If con_expr is true, choose to execute 1, otherwise choose to execute 2. If con_expr is x or z, both must be calculated, and then the calculation result is calculated bit by bit. If one bit is 1, the result is 1, both of which are 0, and the result is 0, otherwise it is X.

Join operator

The join operator is to join two or more small expressions separated by ","in braces to form a large expression.

assigning operator