Signal a: matrix _ index; -the array a[8] is defined, that is, the array elements are a[0], a[ 1], a[2], a[3], a[4], a[5], a[6] and a[7].

Constant R: matrix_index:=( x" 15 ",x"0F", x"0A ",x"06", x"2F ",x"3A", x"4E ",x" 50); -Defined a constant array R[8]

-Just add a subscript when using it, and use downto define the direction, so R[0] is the last item, such as r [0] = x "50 ",r [3] = x "2f" and r [7] = x "15" in the R array.

VHDL, the full name of VHDL, was born in 1982. At the end of 1987, VHDL was recognized as the standard hardware description language by IEEE and US Department of Defense.

Since IEEE- 1076 (abbreviated as version 87), EDA companies have successively launched their own VHDL design environment, or announced that their design tools can interface with VHDL. 1993, IEEE revised VHDL, expanded the content of VHDL from a higher level of abstraction and system description ability, and released a new version of VHDL, namely 1076- 1993 version of IEEE standard, referred to as version 93. VHDL and Verilog, as IEEE industrial standard hardware description languages, have been supported by many EDA companies and become the de facto universal hardware description languages in the field of electronic engineering.

VHDL language is a high-level language for circuit design. It appeared in the late 1980s. Originally developed by the U.S. Department of Defense for the U.S. military to improve the reliability of design and shorten the development cycle, it is a design language with a small scope of use.

The translation of VHDL into Chinese is the hardware description language of ultra-high speed integrated circuits, which is mainly used for the design of digital circuits. Its application in China is mostly used in the design of FPGA/CPLD/EPLD. Of course, in some powerful units, it is also used to design ASIC.