Design principle and its block diagram
1. Composition of digital clock
A digital clock is actually a counting circuit that counts the standard frequency (1HZ). Since the starting time of counting cannot be consistent with the standard time (such as Beijing time), it is necessary to add a time correction circuit to the circuit, and the standard time signal of 1HZ must be accurate and stable. Usually, a digital clock consists of a quartz crystal oscillator circuit. Figure 3- 1 shows the general structure of a digital clock.
Figure 3- 1 digital clock composition block diagram
(1) crystal oscillator circuit
The crystal oscillator circuit provides a square wave signal with stable and accurate frequency of 32768Hz to the digital clock, which can ensure the accuracy and stability of the digital clock. Crystal oscillator circuit is used for analog electronic clock and digital display electronic clock.
(2) Frequency divider circuit
The frequency divider circuit divides the high-frequency square wave signal of 32768Hz by 32,768 () times to obtain a square wave signal of 1hz for the second counter to count. The frequency divider is actually a counter.
(3) Time counting circuit
The time counting circuit consists of a binary counter, a binary counter and a time decimal counter, wherein the binary counter and the binary counter are 60-decimal counters, and the time decimal counter and the time decimal counter are 12 counters according to the design requirements.
(4) decoding drive circuit
The decoding drive circuit converts the 842 1BCD code output by the counter into the logic state required by the digital tube, and provides enough working current to ensure the normal operation of the digital tube.
5] Digital tube
Digital tubes usually include light emitting diode (LED) digital tubes and liquid crystal (LCD) digital tubes. This design provides LED digital tube.
2. The working principle of digital clock
1) crystal oscillator circuit
Crystal oscillator is the core of digital clock, which ensures the accuracy and stability of the clock.
The circuit shown in Figure 3-2 is a digital crystal oscillator circuit with square wave output, which is composed of CMOS NOT gates. In this circuit, CMOS NOT-gate U 1, crystal, capacitor and resistor constitute the crystal oscillator circuit, and U2 realizes the shaping function, converting the approximate sine wave output by the oscillator into an ideal square wave. The output feedback resistor R 1 provides bias for the NOT gate, which makes the circuit work in the amplification region. That is, the function of the NOT gate is similar to that of a high gain inverting amplifier. Capacitors C 1 and C2 form a resonant network with the crystal to control the oscillation frequency, and at the same time provide a phase shift of 180 degrees, thus forming a positive feedback network with the NAND gate and realizing the function of the oscillator. Because the crystal has high frequency stability and accuracy, the stability and accuracy of the output frequency are guaranteed.
The frequency of XTAL crystal is 32768HZ. This component is specially designed for digital clock circuit, and its low frequency is beneficial to reduce the number of frequency dividers.
It can be found from relevant manuals that both C 1 and C2 are 30pF. When higher frequency accuracy and stability are needed, the correction capacitor can be connected and temperature compensation measures can be taken.
Because the input impedance of CMOS circuit is extremely high, the feedback resistance R 1 can be selected as10mΩ. Higher feedback resistance is beneficial to improve the stability of oscillation frequency.
Non-gate circuit can choose 74HC00.
Figure 3-2 COMS crystal oscillator
2) frequency divider circuit
Usually, the crystal oscillator output frequency of digital clock is high. In order to get the second signal input of 1Hz, it is necessary to divide the output signal of the oscillator.
Usually, the circuit to realize the frequency divider is a counter circuit, which is generally realized by multi-level binary counters. For example, the frequency division multiple of the 32768Hz oscillation signal pair 1hz is 32768(2 15), that is, the counter that realizes this frequency division function is equivalent to 15 binary counters. Commonly used binary counters are 74HC393 and so on.
In this experiment, the frequency division circuit is composed of CD4060. CD4060 can achieve the highest frequency division in digital integrated circuits, and also contains the NOT gate required by oscillator circuits, which is more convenient to use.
CD4060 is a binary counter with a count of 14, which can divide the signal of 32768HZ into 2HZ. Its internal block diagram is shown in Figure 3-3. As can be seen from the figure, the clock input of CD4060 has two series-connected NOT gates, so it can directly realize the functions of oscillation and frequency division.
Figure 3-3 Internal Block Diagram of CD 4046
3) Timing device
Time units sometimes include counting, minute counting and second counting.
The hour counting unit is generally a 12 binary counter, and its output is in the form of two-bit 842 1BCD code; Minute counting and second counting units are hexadecimal counters, and its output is also 842 1BCD code.
Generally, 10 base counter 74HC390 is used to realize the counting function of time counting unit. In order to reduce the number of devices, 74HC390 is selected, and its internal logic block diagram is shown in Figure 2.3. This device is a dual 2-5- 10 asynchronous counter, and each counter is equipped with an asynchronous zero clearing terminal (active at high level).
Figure 3-4 Internal Logic Block Diagram of 74hc390 (1/2)
The second bit counting unit is 10 decimal counter, so decimal conversion is not needed. Just connect QA to CPB (falling edge is valid). CPA (invalid falling edge) is connected with 1HZ input signal, and Q3 can be connected with CPA of ten-digit counting unit as the carry-up signal.
The second decimal counter is a hexadecimal counter and needs to be converted into a hexadecimal counter. The circuit connection method for converting 10 decimal counter into hexadecimal counter is shown in Figure 3-5, in which Q2 can be used as an uplink carry signal to connect with CPA of counting unit, with several bits.